| CADAthlon
Brasil 2010 Primeira Maratona Brasileira de Programação para Projeto Automatizado de Circuitos Integrados 19 de julho de 2010, junto ao Crongresso da SBC, PUC-Minas - Belo Horizonte www.inf.ufrgs.br/cadathlonbr |
| Apresentação Regras Gerais Cronograma Inscrições Auxílios Organização Divulgação Problemas Configuração Equipes Novo Local Novo |
Problem 1: Satisfiability Overview: Backtrace search for satisfiability solver Reference: Moskewicz, M. W., Madigan, C. F., Zhao, Y., Zhang, L., and Malik, S. 2001. Chaff: engineering an efficient SAT solver. In Proceedings of the 38th Annual Design Automation Conference (Las Vegas, Nevada, United States). DAC '01. ACM, New York, NY, 530-535. DOI= http://doi.acm.org/10.1145/378239.379017 Problem 2: Analysis & Circuit Design Overview: Clock Skew Optimization Reference: Clock Skew Optimization, John P. Fishburn, IEEE Transactions on Computers, Vol. 39, No. 7, July 1990 Problem 3: Physical Design Overview: Iterative Steiner Heuristics Reference: A New Class of Steiner Tree Heuristics with Good Performance: the Iterated 1-Steiner Approach, Andrew Kahng and Gabriel Robbins, Proc. IEEE International Conference on Computer-Aided Design, November 1990, pp. 428-431 Problem 4: High-Level Synthesis Overview: Register allocation and binding Reference: Kurdahi, F. J. and Parker, A. C. 1987. REAL: a program for REgister ALlocation. In Proceedings of the 24th ACM/IEEE Design Automation Conference (Miami Beach, Florida, United States, June 28 - July 01, 1987). A. O'Neill and D. Thomas, Eds. DAC '87. ACM, New York, NY, 210-215. DOI= http://doi.acm.org/10.1145/37888.37920 Problem 5: Logic Synthesis Overview: Two-level logic minimization Reference: Quine–McCluskey algorithm From Wikipedia, the free encyclopedia Problem 6: Analysis & Circuit Design Overview: Elmore Delay for RC Meshes Reference: L. Vandenberghe, S. Boyd, and A. El Gamal. Optimizing Dominant Time Constant in RC Circuits. IEEE Transactions on Computer Aided Design, 17(2):110-125, February 1998. |
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