IEEE CASS Rio Grande do Sul Chapter

PROGRAMA DL

Distinguished Lecturer Program

CHAMADA DE PALESTRAS

O Capítulo Rio Grande do Sul da IEEE Circuits and Systems inicia um programa piloto de Palestrantes Distinguidos Regionais (Regional DL Program) visando promover palestras nas diferentes instituições da região que possuem sócios da IEEE CASS. Uma palestra em uma cidade deverá ser efetuada por palestrante distinguido proveniente de uma instituição localizada em outra cidade. Os pedidos de palestras devem ser encaminhados pelos representantes instituições da IEEE CASS ao Comitê do Programa DL.

ORGANIZAÇÃO

  • Comitê do Programa DL
  • Carolina Metzler (UFRGS) - c.m.metzler@ieee.org
    Cristina Meinhardt (FURG)
    Cláudio Diniz (UCPel)
  • Coordenador IEEE CASS Rio Grande do Sul Chapter
  • Ricardo Reis (UFRGS)

PALESTRANTES


  • Palestrante:  Alessandro Girardi
  • Instituição:  UNIPAMPA
  • Título da palestra:  Analog Integrated Circuit Design Automation: challenges and strategies
  • Resumo da palestra:  Analog integrated circuit design presents different characteristics from its digital counterparts in terms of number of devices, design methodologies and design automation. As digital electronic systems are modeled using Hardware Description Languages (HDLs), digital design processes are largely removed from technology considerations and from actual physics of the devices. Digital IC design typically focuses on logical correctness, maximization of circuit density, placement, and routing of circuits. The highly automated process produces variable, fab-independent netlists and easily generated layouts that are usually “right the first time”. Analog/mixed-signal designs, on the contrary, are notorious for requiring more than just one prototypation cycle. They typically include a wide variety of primitive devices, such as digital MOS and mid- and high-voltage MOS and bipolar junction transistors (BJT), as well as a host of passive elements that include capacitors, resistors, inductors, varactors, and diodes. These devices are often required to operate under unfriendly environments, where they have to cope with high temperature differences, high voltages, switching noise and interference from neighboring elements. Automatic synthesis of analog integrated circuits is a very hard task due to the complex relationship between technology process parameters, device dimensions, and design specifications. The design of analog building blocks requires circuit parameters to be sized such that design specifications are met or even optimized. An efficient search in the design space is mandatory when hard specifications must be accomplished, mainly for low-voltage and low-power design. The exploration of all transistor operation regions is also fundamental for the search for an optimized circuit. This talk presents the main challenges concerning analog design automation and the strategies for first-time-right design in sub-micrometer fabrication technologies.
  • Short Bio: Alessandro Girardi has graduation at Electrical Engineering from Universidade Federal de Santa Maria (2000), M. Sc. at Computer Science (2002) and PhD at Microelectronics (2007) from Universidade Federal do Rio Grande do Sul. Currently he is with Universidade Federal do Pampa at Alegrete, where he is associated professor. He has experience in Electrical Engineering, with interest on analog integrated circuits, CAD tools, optimization and automatic synthesis.
  • Palestrante:  Cláudio Machado Diniz
  • Instituição:  UCPel
  • Título da palestra:  Hardware Accelerators for the High Efficiency Video Coding (HEVC) Standard
  • Resumo da palestra:  Digital video applications are widespread in every consumer electronic devices. Ultra-high resolutions videos (e.g. 8k×4k and 4k×2k resolutions) are gaining importance in the market. The development of an improved video coding standard with higher efficiency for higher resolution led to the High Efficient Video Coding (HEVC), H.265, published in 2013. This new video coding standard reaches up to approximately double compression efficiency of H.264/AVC standard for similar video quality, due to its sophisticated block partitioning schemes and novel coding algorithms. Its higher compression efficiency comes with a significant increase in computational effort in the video codecs. Real-time HEVC encoding of UHD resolution videos is a challenge, especially considering mobile video-capable hardware devices that must consume lower energy to increase battery life. This energy efficiency requirement for future multimedia processors is requiring hardware architecture innovations to integrate multi-core processors with many on-chip hardware accelerators for compute-intensive tasks of the video encoder/decoder. This talk covers recent dedicated hardware accelerators which are more energy efficient than general purpose processors in performing video tasks. A detailed analysis of HEVC video coding application is presented first to identify the most compute-intensive tasks of video codec that are key blocks for hardware acceleration. In the end we point to significant future challenges to design low-power HEVC video codec systems.
  • Short Bio: Cláudio Diniz received his B.S. degree in Computer Engineering from the Federal University of Rio Grande (FURG), Rio Grande, Brazil, and the M.S. and Ph.D. degrees in Computer Science from the Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil. Since 2015 he is Assistant Professor at the Catholic University of Pelotas (UCPel). Previously, he was a Ph.D. internee at the Karlsruhe Institute of Technology, Karlsruhe, Germany. He worked as a Digital Designer at CEITEC S.A Semiconductors. Researches since 2007 in the fields of architectures for computational systems, embedded systems and microelectronics, developing algorithms, architectures and integrated circuits for video coding (H.264/AVC and H.265/HEVC standards).
  • Palestrante:  Guilherme Bontorin
  • Instituição:  URI-FW
  • Título da palestra:  Microelectronics for Biomedical Applications
  • Resumo da palestra:  The progress of Neural Prostheses and Brain Machine Interfaces is blocked mainly by the reduced knowledge of the natural evolution of the living neural tissue both in sane and ill conditions. In this talk we will address some main points about the variability of living tissue and focus on many approaches where Microelectronics can help the development of fundamental biomedical science and the design neural prostheses.
  • Short Bio: Guilherme Bontorin received his Master's degree in Electronics Engineering and Microelectronics from the ENSEIRB (France) joint with the University of Bordeaux (France) in 2006. In 2010, he received his PhD degree in Microtechnology from the University of Neuchatel (Switzerland) joint with the PhD degree in Electronics from the University of Bordeaux. He made a first post-doc at LIRMM/University of Montpellier (France) on Neuralprostheses dependability from 2010 to 2012. This has been followed by a second post-doc at UFRGS (Brazil)on biomimedical neural networks on silicon, from 2013 to 2016. Since 2016 he is a professor at URI-FW at Brazil (Universidade Regional Integrada do Alto Uruguai e das Missões, campus Frederico Westphalen) teaching courses on electronics, computer architecture, embedded systems, and artificial intelligence. His research interest is focused on microelectronics for biomedical applications, including Dependable Neuralprostheses, Analog/Mixed/Digital Integrated Circuits Design, Bioelectronic Closed-loop systems, Biomimetic Neural Networks, and Artificial Intelligence.
  • Palestrante:  José Luís Güntzel
  • Instituição:  UFSC
  • Título da palestra:  TBD
  • Resumo da palestra:  TBD
  • Short Bio: TBD
  • Palestrante:  Paolo Rech
  • Instituição:  UFRGS
  • Título da palestra:  Reliability Issues in Current and Future Supercomputers
  • Resumo da palestra:  Modern Supercomputers are composed of thousands of Graphics Processing Units (GPUs) that work in parallel. Titan, the world's second fastest supercomputer for open science in 2015, consists of more than 18,000 GPUs used by scientists from various domains such as astrophysics, fusion, climate, and combustion. Due to the large-scale and the long duration, these scientific applications may encounter interruptions due to system failures as well as Silent Data Corruptions (SDCs). Therefore, while the performance improvement achievedvia the inherent parallelism available in GPUs is necessary to expedite the scientific discovery process, it is equally critical that applications are able to cope with system failures during their execution, without losing all of the work.As we will show in the talk that the newest GPU cores are sensitive to radiation-induced errors, including those from the terrestrial neutron radiation environment. Experimental data obtained during three years of radiation experiments on current GPUs and the analysis of Titan field data will be presented and discussed. A detailed analysis of the causes and effects of radiation-induced failures in supercomputers will be provided using a wide set of parallel applications as case studies. Experimental data will be used to show the benefit of enabling ECC on GPUs main memory structures and compare its efficiency with duplication and Algorithm Based Fault Tolerance one. Finally, novel code optimizations to reduce the time-to-solution of specific parallel algorithms are continuously implemented. As experimentally demonstrated, codes optimizations increase the code sensitivity but may reduce the execution time in a way that increase the overall system reliability.
  • Short Bio: Paolo Rech received his master and Ph.D. degrees from Padova University, Padova, Italy, in 2006 and 2009, respectively. His studies included radiation tests and the effect of neutrons, protons, and alpha particles on programmable devices like FPGAs and Systems On Chip. He was a Post Doc at LIRMM, Montpellier, France from 2010 to 2012, working on radiation effects onelectronic devices at high altitudes. He is currently an associate professor atthe Federal University of Rio Grande do Sul, Porto Alegre, RS, Brazil. Recently, he started collaborations with NVIDIA, AMD, and Los Alamos National Lab to evaluate and mitigate the radiation-induced effects in devices designed for large-scale HPC centers.
  • Palestrante:  Paulo Butzen
  • Instituição:  FURG
  • Título da palestra:  TBD
  • Resumo da palestra:  TBD
  • Short Bio: TBD
  • Palestrante:  Fabian Luis Vargas
  • Instituição:  PUC-RS
  • Título da palestra:  Combined Effects of Ionizing Radiation, Accelerated Aging and Electromagnetic Interference in Modern ICs: Comprehension and Current Solutions
  • Resumo da palestra:  Technology scaling, which made electronics accessible and affordable for almost everyone on the globe, has advanced IC and electronics since sixties. Nevertheless, it is well recognized that such scaling has introduced new (and major) reliability challenges to the semiconductor industry. This tutorial addresses the background mechanisms impacting reliability of very deep submicron (VDSM) integrated circuits (ICs). Issues like ionizing radiation (Total-Ionizing Dose: TID and Single-Event Effects: SEEs), accelerated aging and electromagnetic interference (EMI) are presented and their combined effects on the reliability of modern ICs is discussed. Reliability failure mechanisms for radiation and aging, the way they are modeled and how they are impacting IC lifetime will be covered. Laboratory test setup and recent results from experimental measurements are described. Classic design solutions to counteract with TID, SEEs, aging and EMI in VDSM ICs as well as the recent achievements on the development of on-chip sensors for leveraging robustness of embedded systems for critical applications are introduced.
  • Short Bio: Fabian Vargas obtained his Ph.D. Degree in Microelectronics from the Institut National Polytechnique de Grenoble (INPG), France, in 1995. At present, he is Full Professor at the Catholic University (PUCRS) in Porto Alegre, Brazil.His main research domains involve the HW-SW co-design and test of system-on-chip (SoC) for critical applications, system-level design methodologies for radiation, accelerated aging and electromagnetic compatibility, and embedded sensor design for characterization, reliability and aging binning.Among several activities, Prof. Vargas has served as Technical Committee Member or Guest-Editor in many IEEE-sponsored conferences and journals. He holds 6 BR and international patents, co-authored a book and published over 200 refereed papers. Prof. Vargas is associate researcher of the BR National Science Foundation since 1996.He co-founded the IEEE-Computer Society Latin American Test Technology Technical Council (LA-TTTC) in 1997 and the IEEE Latin American Test Symposium - LATS (former Latin American Test Workshop - LATW) in 2000. Prof. Vargas received for several times the Meritorious Service Award of the IEEE Computer Society for providing significant services as chair of the IEEE Latin American Regional TTTC Group and the LATS. Prof. Vargas is a Golden Core Member of the IEEE Computer Society.

INSCRIÇÃO

O capítulo do Circuits and Systems Society (CASS) Rio Grande do Sul é uma subunidade regional da IEEE CASS que promove atividades de interesse desta sociedade nos estados da região Sul do Brasil (RS, SC, e PR).

É um dos capítulos mais expressivos em número de membros em comparação com o número de membros da IEEE CASS no Brasil. A fim de incentivar novos membros e de promover a pesquisa desenvolvida em diferentes instituições onde há sócios da IEEE CASS na região Sul do país, foi criado o programa de Palestrantes Distinguidos Regionais (Regional DL Program). Deste modo, palestrantes poderão receber custeio (hospedagem e transporte) para o deslocamento à instituição a qual será feita a palestra.

Para participar do programa DL regional é necessário que os representantes institucionais CASS inscrevam o palestrante e a sua solicitação será encaminhada ao comitê de organização (através do e-mail c.m.metzler@ieee.org). Para enviar propostas de palestras são necessárias as seguintes informações:

Nome do proponente:
Número IEEE do proponente:
Nome do palestrante:
Short-CV do palestrante:
Título da palestra:
Resumo do assunto da palestra:
Data da palestra:
Datas de chegada e de saída do palestrante:
Local da palestra:
Estimativa de custo com translado, hospedagem e alimentação do palestrante:

É importante que o palestrante proposto seja sócio da CASS e que possua título de doutor.