IEEE CASS Seasonal School on

Physical Design Automation

July 31 to August 5, 2017


Auditório Centro de Eventos do Instituto de Informática UFRGS

Porto Alegre, Brazil

About

The 2017 Seasonal School on Physical Design Automation aims to offer a set of talks on key topics of physical design for integrated circuits in modern and upcoming technologies. It should represent current and future challenges that are faced by industry and academia for the implementation of ever more complex circuits and systems. We want to promote discussion on hot topics and cover fundamental algorithms and computational methods in the area, so that the attendance can leverage their comprehension and capabilities, while also attracting new students and researchers to the right problems. The courses will be given by prominent international researchers with extensive expertise in their fields. Each course should be given in 2h40m, in two parts of 1h20m (exceptions can be considered according to particular needs). Associated to the school, a book will be proposed, for which every speaker is invited to write a chapter, although the participation is not mandatory, and additional chapters or splitting/merging of chapters can be considered.


The main topics to be covered by the school will include:

  • Global and Detailed placement
  • Gate sizing
  • Routing and routability
  • Tools for 3D architectures
  • Layout manufacturability
  • Clock routing buffer/wire sizing
  • Machine Learning for EDA
  • Layout Design Automation

The School's technical program will include 8 courses of 2h40min each, divided into two parts of 1h20min each, with a coffee break. There will be a panel each day to involve participants into discussions related to the subjects covered. In the afternoon coffee break, there is also a provision for poster sessions related to the school topics. The corresponding call for posters is being prepared. As a social event, the school will include a gala dinner.

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ORGANIZATION

General Chair
Ricardo Reis, UFRGS, Brazil
Finance Chair
José Rodrigo Azambuja, UFRGS
Program Chairs
Patrick Madden, Professor at SUNY Binghamton, USA
Marcelo Johann, Professor at UFRGS
Poster Session Chair
Jucemar Monteiro, UFRGS
Local Organization
Mateus Fogaça (chair), UFRGS
Jody matos, UFRGS
Augusto Neutzling, UFRGS
IEEE CASS Liaison
Ricardo Reis, UFRGS, Brazil
IEEE CEDA Liaison
José Guntzel, UFSC, Brazil

PROGRAM

Monday - July 31
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  • Palestrante: Prof. William Swartz (TimberWolf and University of Texas at Dallas)
  • Resumo: These lectures will open with a general review of computer aided design (CAD) flow for integrated circuits. An overview and history of the detailed routing process will be described. The lectures will first focus on the algorithms of a single detailed route, including line-search, breadth-first search, Lee maze routing, and A-star. Basic design rules will be introduced leading to the introduction of multiple pin connections as well as multiple networks. The disjoint-set data structure will be introduced and how it can aid detailed routing. Next, algorithms which route a forest of nets will be presented include channel routing, switch box routing, graph-conflict resolution, ripup-and-reroute, negotiation, track, and spine routers. The lecture concludes with real world problems and techniques such a net beautification, pin accessibility checking, advanced design rules, and coloring algorithms for multiple step lithography patterning.
  • Bio: William Swartz received his undergraduate degree (BSEE) from the University of Pennsylvania. His M.S. was acquired at The University of Texas at Arlington. In 1993 he received his Ph.D from Yale University in the field of Electrical Engineering. Throughout his career William (Bill) has worked in the semiconductor industry. His main focus has been on analog and digital circuit design. He developed and wrote a complete placement and routing package called TimberWolf. The success of this software has enabled the formation of TimberWolf Systems, Inc. which he currently serves as the principle software designer. Since 2010, he has been on the faculty of the University of Texas at Dallas as senior lecturer. He teaches course on computer architecture, microprocessors, hardware design languages, and advanced digital logic design.
  • Palestrante: Prof. William Swartz (TimberWolf and University of Texas at Dallas)
  • Resumo: These lectures will open with a general review of computer aided design (CAD) flow for integrated circuits. An overview and history of the detailed routing process will be described. The lectures will first focus on the algorithms of a single detailed route, including line-search, breadth-first search, Lee maze routing, and A-star. Basic design rules will be introduced leading to the introduction of multiple pin connections as well as multiple networks. The disjoint-set data structure will be introduced and how it can aid detailed routing. Next, algorithms which route a forest of nets will be presented include channel routing, switch box routing, graph-conflict resolution, ripup-and-reroute, negotiation, track, and spine routers. The lecture concludes with real world problems and techniques such a net beautification, pin accessibility checking, advanced design rules, and coloring algorithms for multiple step lithography patterning.
  • Bio: William Swartz received his undergraduate degree (BSEE) from the University of Pennsylvania. His M.S. was acquired at The University of Texas at Arlington. In 1993 he received his Ph.D from Yale University in the field of Electrical Engineering. Throughout his career William (Bill) has worked in the semiconductor industry. His main focus has been on analog and digital circuit design. He developed and wrote a complete placement and routing package called TimberWolf. The success of this software has enabled the formation of TimberWolf Systems, Inc. which he currently serves as the principle software designer. Since 2010, he has been on the faculty of the University of Texas at Dallas as senior lecturer. He teaches course on computer architecture, microprocessors, hardware design languages, and advanced digital logic design.
  • Palestrante: Prof. José Luís Güntzel (UFSC)
  • Resumo: Contemporary VLSI fabrication technologies provide several metal layers. To reduce resistance and coupled capacitance, the upper layers are thicker, wider and more spaced than the lower ones, resulting in less routing resources. After global routing, incremental layer assignment can be used to improve the circuit timing by properly selecting critical interconnect segments to be routed in the faster wires on upper layers. Existing techniques based on net-by-net iterative improvement may get stuck at locally-optimal solutions depending on net ordering. Recent techniques overcome such drawback through the simultaneous iterative improvement of all nets. However, they rely on objective functions that may guide the optimization off critical paths. Moreover, all techniques reported so far rely on simplified, overly pessimistic timing models. In this talk we show that flow conservation conditions can be exploited not only to properly deal with several critical nets simultaneously, but also to decouple the layer assignment from the timing analysis, thus enabling the use of an industrial signoff timing engine to guide the search. The presented technique leads to less timing violations in terms of total negative slack than previous techniques with similar overhead in number of vias.
  • Bio: José Luís Güntzel received the Electrical Engineering degree from the Federal University of Rio Grande do Sul (UFRGS), Brazil, in 1990 and the M.Sc. and Ph.D. degrees in Computer Science also from UFRGS in 1993 and 2000, respectively. In 1996 he spent a one-year doctoral stage in the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM), France. From 2002 to 2007 he served as an Assistant Professor at the Federal University of Pelotas (UFPel), Pelotas, Brazil. Currently, he is an Associate Professor at the Federal University of Santa Catarina (UFSC), Florianópolis, Brazil. His research interests include Physical Design Automation, VLSI architectures for high-resolution video coding, design of energy-efficient systems-on-chip (SoCs) and VLSI architectures for digital signal processing. Dr. Güntzel is a member of the Brazilian Computer Society (SBC), Brazilian Microelectronics Society (SBMicro), IEEE Circuits and Systems Society and IEEE Signal Processing Society. Currently, he is the chair of the IEEE Council for Electronic Design Automation (CEDA) Brazil Chapter.
  • Palestrante: Renan Netto (UFSC)
  • Resumo: Similarly to game engines, physical design tools must handle huge amounts of data. Although the game industry has been employing modern software development concepts such as data-oriented design, most physical design tools still relies on object-oriented design. Differently from object-oriented design, data-oriented design focuses on how data is organized in memory and can be used to solve typical object-oriented design problems. However, its adoption is not trivial because most software developers are used to think about objects' relationships rather than data organization. The entity-component design pattern can be used as an efficient alternative. It consists in decomposing a problem into a set of entities and their components (properties). This presentation discusses the main data-oriented design concepts, how they improve software quality and how they can be used in the context of physical design problems. In order to evaluate this programming model, we implemented an entity-component system using the open-source library Ophidian. Experimental results for three physical design tasks show that data-oriented design is much faster than object-oriented design for problems with good data locality, while been only sightly slower for other kinds of problems.
  • Bio: Renan Netto received its Computer Science degree from the Federal University of Santa Catarina (UFSC), Brazil, in 2015, and the M.Sc degree in Computer Science also from UFSC in 2017. He is currently a Ph.D. student in Computer Science in the same university. His research interests include Physical Design Automation, mainly placement and legalization algorithms.

Tuesday - Aug 1
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  • Palestrante: Prof. Laleh Behjat (University of Calgary, Canadá)
  • Resumo: In the first part of this course, we will discuss the main components of mathematical optimization problems and what is the description of a convex function. Then, we will discuss modeling techniques for solving problems seen in CAD, including placement, routing and clock networks, as large scale convex optimization problems. Each problem will be modelled with a different format in mind: placement will be modelled as convex optimization problem, the routing problem will be formulated as an integer linear programming problem and clock networks will be modelled as a geometric programming problem.In the second part of the course, we will walk through methodologies for solving the formulated optimization problems: equality constrained problems, Lagrangian multipliers, integer linear programming and geometric programming.At the end of this workshop the participants will know how to formulate several different CAD problems as well as optimization strategies for solving them. The workshop is an interactive workshop and the students will be asked to work on teams to solve different problems.
  • Bio: Dr. Laleh Behjat is a professor at the University of Calgary in Alberta Canada. Her research mainly focuses on applying mathematical techniques for solving physical design problems. She has won several awards for her work on the development of software tools for computer engineering including ISPD 2014 Placement Contest 1st place, ISPD 2015 Placement Contest 2nd place and Schulich School of Engineering Research Award. Her research team She is currently supervising 9 graduate and 2 undergraduate studentsIn addition, Dr. Behjat has a passion for increasing the statues of women in Science, technology, engineering and mathematics (STEM). Dr. Behjat was the recipient of 2015 Association of Professional Engineers and Geoscientists of Alberta (APEGA) Women in Engineering Champion Award, and Association of Computing Machinery, Special Interest Group in Design Automation Service Award in 2014.
  • Palestrante: Prof. Mark Po-Hung Lin (National Chung Cheng University,Taiwan)
  • Resumo: Analog, mixed-signal, and RF integrated circuits play an important role in many modern emerging system-on-chip (SoC) and internet-of-things (IoT) applications. With the expansion of the markets of those applications, the demands of analog/mixed-signal ICs have been dramatically increased. However, the development of analog electronic design automation (EDA) tools is still farther behind that of digital EDA tools. As a result, analog/mixed-signal/RF IC design, especially the layout design, is still a manual, time-consuming, and error-prone task. In order to reduce design cycles of analog/mixed-signal/RF ICs for large varieties of emerging applications, it is essential to develop novel analog/mixed-signal/RF IC layout deign methodologies, algorithms, and tools. This lecture will summarize the research progress during the past decade, address new layout design challenges in advanced technology nodes, and hopefully facilitate more research activities in layout synthesis for analog, mixed-signal, and RF ICs.
  • Bio: Mark Po-Hung Lin received the Ph.D. degree in the Graduate Institute of Electronics Engineering, National Taiwan University (NTU), Taiwan. He was with SpringSoft, Inc. (acquired by Synopsys, Inc. in 2012) during 2000–2007, where he led a team to initiate the Laker Analog Prototyping Tool for improving layout productivity. He has been with the Department of Electrical Engineering, National Chung Cheng University, Chiayi, Taiwan, where he is going to be a Full Professor in August 2017. He has also been a Visiting Scholar with the University of Illinois at Urbana-Champaign, Champaign, IL, USA, during 2007–2009, a Humboldt Research Fellow with the Technical University of Munich (TUM), Germany, during 2013–2015, and a JSPS Invitation Fellow with Osaka University, Japan, in 2016. His research interests include design automation for analog/mixed-signal/RF integrated circuits and low-power resilient circuit and system design optimization. He has served in the technical program committees of premier EDA conferences, including DAC, DATE, ASP-DAC, and ISPD. He received IEEE Tainan Section Macronix Award, IEEE Tainan Section Best GOLD Member Award, Humboldt Research Fellowship for Experienced Researchers, JSPS Invitation Fellowship for Research in Japan, Distinguished Young Scholar Award of Taiwan IC Design Society, and Distinguished Young Faculty Award of National Chung Cheng University.
  • Palestrante: Prof. Ulrich Brenner (University of Bonn, Germany)
  • Resumo: Placement is one of the crucial steps in physical design of VLSI chips. The decisions made in this phase have a strong influence on all later optimization steps. The bad news is that the instances can be large and that any reasonable formulation of the placement problem turns out to be NP-hard.We will give an introduction into VLSI placement under theoretical and practical aspects. To this end, we will discuss a variety of objective functions and constraints that have to be considered by placement algorithms.We will give an overview of theoretical results concerning placement. Most of them are hardness proofs but for some special cases, polynomial algorithms with non-trivial approximation ratios are known.Placement is a discrete problem (which makes it a hard task) but as long as we are only interested in a rough global arrangement of the cells, often continuous optimization methods can be applied to it. We will see several algorithm of great practical relevance that are based on such a relaxation to a continuous problem. We will also give an overview of practical ways how more complex goals like timing, routability and stability can be reflected.When it comes to legalization, all overlaps between cells have to be removed and discrete decisions are unavoidable. For standard cells, these decisions have a limited effect, so we will see that reasonable heuristics are typically good enough. However, for large macros any decision of their relative positions can change the whole design drastically. Therefore, we will discuss ways to enumerate arrangements of macros for optimization of standard objective functions. We will also discuss the limitations of these approaches. For example, the timing optimization during macro placement is a very challenging task because it enforces a real mixed-size placement.
  • Bio: Ulrich Brenner received the Diploma and PhD. degrees from the University of Bonn, Germany in 2000 and 2005, respectively.He is currently with the Research Institute for Discrete Mathematics, University of Bonn. His research interests include combinatorial optimization and its application in VLSI design. He is one of the main developers of BonnPlace. BonnPlace is part of the BonnTools, a set of tools for physical design that have been developed at the University of Bonn in a long-term cooperation with IBM.
  • Palestrante: Prof. Ulrich Brenner (University of Bonn, Germany)
  • Resumo: Placement is one of the crucial steps in physical design of VLSI chips. The decisions made in this phase have a strong influence on all later optimization steps. The bad news is that the instances can be large and that any reasonable formulation of the placement problem turns out to be NP-hard.We will give an introduction into VLSI placement under theoretical and practical aspects. To this end, we will discuss a variety of objective functions and constraints that have to be considered by placement algorithms.We will give an overview of theoretical results concerning placement. Most of them are hardness proofs but for some special cases, polynomial algorithms with non-trivial approximation ratios are known.Placement is a discrete problem (which makes it a hard task) but as long as we are only interested in a rough global arrangement of the cells, often continuous optimization methods can be applied to it. We will see several algorithm of great practical relevance that are based on such a relaxation to a continuous problem. We will also give an overview of practical ways how more complex goals like timing, routability and stability can be reflected.When it comes to legalization, all overlaps between cells have to be removed and discrete decisions are unavoidable. For standard cells, these decisions have a limited effect, so we will see that reasonable heuristics are typically good enough. However, for large macros any decision of their relative positions can change the whole design drastically. Therefore, we will discuss ways to enumerate arrangements of macros for optimization of standard objective functions. We will also discuss the limitations of these approaches. For example, the timing optimization during macro placement is a very challenging task because it enforces a real mixed-size placement.
  • Bio: Ulrich Brenner received the Diploma and PhD. degrees from the University of Bonn, Germany in 2000 and 2005, respectively.He is currently with the Research Institute for Discrete Mathematics, University of Bonn. His research interests include combinatorial optimization and its application in VLSI design. He is one of the main developers of BonnPlace. BonnPlace is part of the BonnTools, a set of tools for physical design that have been developed at the University of Bonn in a long-term cooperation with IBM.
  • Palestrante: Prof. André Reis (UFRGS)
  • Resumo: Logic synthesis most powerful transformations occur at early steps, that abstract the target technology. At the same time, most design costs are caused by technology issues. In this talk we discuss how to bring technology information into early steps of design flow. Our proposal is based on some enablers, including: (1) Use of placed AIGs, with explicit inverters, (2) Using KL-cuts as a tool for logic aware partitioning, (3) Treating logic computation and logic (signal) distribution distinctly, and (4) relying on global timing budget expressed through local design constraints (SDC files). Based on these enablers we describe a new design flow, that has novel design problems aiming at seamless introducing technology information throughout the flow, starting at early steps.
  • Bio: André Reis is a Professor at the Institute of Informatics, UFRGS, Brazil, since 2000. He is a senior member of IEEE and ACM, and published more than 200 academic papers and he has also 10 granted USA patents. He received best paper awards from IFIP VLSI 1997, SBCCI 2013 and IWLS 2015. Prof. Andre Reis is actively involved with the organization of ACM/IEEE International Workshop on Logic and Synthesis, where he acted in several positions, including general chair (Mountain View, 2015), program chair (Austin, 2016), finance chair (Austin, 2017) and he is a member of the steering committee (2016 to 2020). Andre Reis is an advisor for Nangate Inc since 2005, and coordinated cooperation directly between UFRGS and Nangate, as well as among Nangate, UFRGS and other six european partners (Nangate, UFRGS, IMEC, Thales, ST Microelectronics, UPC, Polimi and Leading Edge) during the european FP7 project Synaptic. Andre Reis is interested in EDA, with special interests in (1) mixing logic and physical synthesis to improve the overall design flow, (2) using general purpose optimization solvers (SAT, SMT, ILP), (3) scalability for large designs (through parallelism and EDA 3.0). Additional interests include technical writing, and Prof. Andre Reis teaches a course on scientific writing including articles and patents, having extensive experience with intellectual property legal aspects. Prof. Andre Reis wrote more than 500 poems, including one that was selected for the highly selective Poemas no Onibus (Poetry in Public Transportation) contest.

Wednesday - Aug 2
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  • Palestrante: Prof. Laleh Behjat (University of Calgary, Canadá)
  • Resumo: In the first part of this course, we will discuss the main components of mathematical optimization problems and what is the description of a convex function. Then, we will discuss modeling techniques for solving problems seen in CAD, including placement, routing and clock networks, as large scale convex optimization problems. Each problem will be modelled with a different format in mind: placement will be modelled as convex optimization problem, the routing problem will be formulated as an integer linear programming problem and clock networks will be modelled as a geometric programming problem.In the second part of the course, we will walk through methodologies for solving the formulated optimization problems: equality constrained problems, Lagrangian multipliers, integer linear programming and geometric programming.At the end of this workshop the participants will know how to formulate several different CAD problems as well as optimization strategies for solving them. The workshop is an interactive workshop and the students will be asked to work on teams to solve different problems.
  • Bio: Dr. Laleh Behjat is a professor at the University of Calgary in Alberta Canada. Her research mainly focuses on applying mathematical techniques for solving physical design problems. She has won several awards for her work on the development of software tools for computer engineering including ISPD 2014 Placement Contest 1st place, ISPD 2015 Placement Contest 2nd place and Schulich School of Engineering Research Award. Her research team She is currently supervising 9 graduate and 2 undergraduate studentsIn addition, Dr. Behjat has a passion for increasing the statues of women in Science, technology, engineering and mathematics (STEM). Dr. Behjat was the recipient of 2015 Association of Professional Engineers and Geoscientists of Alberta (APEGA) Women in Engineering Champion Award, and Association of Computing Machinery, Special Interest Group in Design Automation Service Award in 2014.
  • Palestrante: Prof. Mark Po-Hung Lin (National Chung Cheng University,Taiwan)
  • Resumo: Analog, mixed-signal, and RF integrated circuits play an important role in many modern emerging system-on-chip (SoC) and internet-of-things (IoT) applications. With the expansion of the markets of those applications, the demands of analog/mixed-signal ICs have been dramatically increased. However, the development of analog electronic design automation (EDA) tools is still farther behind that of digital EDA tools. As a result, analog/mixed-signal/RF IC design, especially the layout design, is still a manual, time-consuming, and error-prone task. In order to reduce design cycles of analog/mixed-signal/RF ICs for large varieties of emerging applications, it is essential to develop novel analog/mixed-signal/RF IC layout deign methodologies, algorithms, and tools. This lecture will summarize the research progress during the past decade, address new layout design challenges in advanced technology nodes, and hopefully facilitate more research activities in layout synthesis for analog, mixed-signal, and RF ICs.
  • Bio: Mark Po-Hung Lin received the Ph.D. degree in the Graduate Institute of Electronics Engineering, National Taiwan University (NTU), Taiwan. He was with SpringSoft, Inc. (acquired by Synopsys, Inc. in 2012) during 2000–2007, where he led a team to initiate the Laker Analog Prototyping Tool for improving layout productivity. He has been with the Department of Electrical Engineering, National Chung Cheng University, Chiayi, Taiwan, where he is going to be a Full Professor in August 2017. He has also been a Visiting Scholar with the University of Illinois at Urbana-Champaign, Champaign, IL, USA, during 2007–2009, a Humboldt Research Fellow with the Technical University of Munich (TUM), Germany, during 2013–2015, and a JSPS Invitation Fellow with Osaka University, Japan, in 2016. His research interests include design automation for analog/mixed-signal/RF integrated circuits and low-power resilient circuit and system design optimization. He has served in the technical program committees of premier EDA conferences, including DAC, DATE, ASP-DAC, and ISPD. He received IEEE Tainan Section Macronix Award, IEEE Tainan Section Best GOLD Member Award, Humboldt Research Fellowship for Experienced Researchers, JSPS Invitation Fellowship for Research in Japan, Distinguished Young Scholar Award of Taiwan IC Design Society, and Distinguished Young Faculty Award of National Chung Cheng University.
  • Palestrante: Prof. Andrew B. Kahng (University of California at San Diego, USA)
  • Resumo: This two-part class covers issues that physical design researchers must comprehend in order to be successful in research, and to make an impact with their work. In Part I, I will discuss research mindsets, “patterns” and platforms. Some aspects include: (i) avoiding incrementality in the guise of novelty, (ii) establishing research enablements (libraries, flows, designs, etc.) and figures of merit that can adequately support claims of relevance and value, and (iii) methodology for validation and reporting.In Part II, I will discuss the role of machine learning techniques in IC physical design, as the industry addresses severe schedule, resource and quality-of-results challenges in today’s late-CMOS era. Opportunities and value propositions for data mining, machine learning, and deep learning in physical design abound. Some examples include: (i) achieving faster design convergence through new predictors of downstream flow outcomes, (ii) removing unnecessary design and modeling margins through new correlation mechanisms, and even (iii) optimizing the usage of EDA tool licenses and available schedule.
  • Bio: Andrew B. Kahng is Professor of CSE and ECE at UC San Diego, where he holds the endowed chair in High-Performance Computing. He has served as visiting scientist at Cadence (1995-1997) and as founder/CTO at Blaze DFM (2004-2006). He is the coauthor of 3 books and over 400 journal and conference papers, holds 33 issued U.S. patents, and is a fellow of ACM and IEEE. He has served as general chair of DAC, ISQED, ISPD and other conferences. His research interests include IC physical design and performance analysis, the IC design-manufacturing interface, combinatorial algorithms and optimization, and the roadmapping of systems and technology.
  • Palestrante: Prof. Patrick H. Madden (State University of New York at Binghamton, USA)
  • Resumo: Following global placement, a circuit must be legalized, and then detail placement is performed. The algorithmic approaches used at the small scale are frequently combinatorial in nature — branch-and-bound, dynamic programming, and in some cases, greedy algorithms. In this talk, we will cover advanced applications of dynamic programming to legalization, detailed placement, and also touch on gate sizing problems. Window-based branch-and-bound methods will be presented, along with simple greedy algorithms that are surprisingly effective for mixed-size placement legalization.The talk will then consider current work on combinatorial optimization, using a novel hybrid of enumeration, greedy tree pruning, and fast multi-dimensional Pareto front algorithms. The goal of the current work is to develop an extensible general purpose combinatorial solver, allowing a unification of different physical design subproblems (e.g., detailed placement and gate sizing) into a single step.
  • Bio: Patrick H. Madden is an associate professor of computer science at Binghamton University, he received a PhD in computer science from UCLA in 1998. His research focus has been on VLSI physical design automation, with an emphasis on placement and routing. Over the past few years, his focus has shifted to general purpose combinatorial optimization, expanding from design automation into biotech areas. He is an active in the ACM, chairing ACM/SIGDA, the ACM SIG Governing Board. He has served on the program committees and steering committees of all the major design automation conferences. In addition to his research and teaching activities, he also develops apps for mobile devices, and is a mediocre guitarist.

Thursday - Aug 3
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  • Palestrante: Prof. Evangeline Young (Chinese University of Hong Kong )
  • Resumo: As technology scales down to deep submicron nodes, different kinds of lithography techniques like optical proximity correction, multiple patterning, E-beam lithography, etc. are needed to ensure a layout manufacturable. Multiple patterning lithography (MPL) technology divides one layout into multiple masks and repeats the litho-etch process. E-beam lithography will project the layout characters onto the wafer directly with electron beams. To order to enable successful manufacturing, we need to take into account these lithography techniques and the constraints imposed during physical design. Considering those constraints brought by the lithography processes during placement, detailed placement and detailed routing are essential in order to explore a larger solution space for layout decomposition or character selection etc, to better optimize the placement objectives. In this talk, the speaker will give an introduction to design for manufacturability and how placers and routers can take into account different lithography issues in their design and optimization process.
  • Bio: Evangeline Young received her B.Sc. degree in Computer Science from The Chinese University of Hong Kong (CUHK). She received her Ph.D. degree from The University of Texas at Austin. She is currently a professor in the Department of Computer Science and Engineering in CUHK. Her research interests include algorithms, optimization and VLSI CAD. She works actively on placement, routing, DFM and EDA on Physical Design. Dr. Young has served in the program committees of conferences including ISPD, DAC, ICCAD, ASP-DAC, DATE etc. She also serves on the editorial boards of IEEE TCAD, ACM TODAES and Integration, the VLSI Journal. Her research group has won the ISPD and the SLIP Best Paper Awards in 2017. They have also won championships and prizes in many renown EDA contests, including the ICCAD 2016, 2015, 2013 and 2012 CAD Contests, the ISPD 2017 and 2016 Contests on Routability Driven FPGA Placement, the DAC 2012 and ISPD 2011 Routability-driven Placement Contests and the ISPD 2010 High Performance Clock Network Synthesis Contest.
  • Palestrante: Prof. Evangeline Young (Chinese University of Hong Kong )
  • Resumo: As technology scales down to deep submicron nodes, different kinds of lithography techniques like optical proximity correction, multiple patterning, E-beam lithography, etc. are needed to ensure a layout manufacturable. Multiple patterning lithography (MPL) technology divides one layout into multiple masks and repeats the litho-etch process. E-beam lithography will project the layout characters onto the wafer directly with electron beams. To order to enable successful manufacturing, we need to take into account these lithography techniques and the constraints imposed during physical design. Considering those constraints brought by the lithography processes during placement, detailed placement and detailed routing are essential in order to explore a larger solution space for layout decomposition or character selection etc, to better optimize the placement objectives. In this talk, the speaker will give an introduction to design for manufacturability and how placers and routers can take into account different lithography issues in their design and optimization process.
  • Bio: Evangeline Young received her B.Sc. degree in Computer Science from The Chinese University of Hong Kong (CUHK). She received her Ph.D. degree from The University of Texas at Austin. She is currently a professor in the Department of Computer Science and Engineering in CUHK. Her research interests include algorithms, optimization and VLSI CAD. She works actively on placement, routing, DFM and EDA on Physical Design. Dr. Young has served in the program committees of conferences including ISPD, DAC, ICCAD, ASP-DAC, DATE etc. She also serves on the editorial boards of IEEE TCAD, ACM TODAES and Integration, the VLSI Journal. Her research group has won the ISPD and the SLIP Best Paper Awards in 2017. They have also won championships and prizes in many renown EDA contests, including the ICCAD 2016, 2015, 2013 and 2012 CAD Contests, the ISPD 2017 and 2016 Contests on Routability Driven FPGA Placement, the DAC 2012 and ISPD 2011 Routability-driven Placement Contests and the ISPD 2010 High Performance Clock Network Synthesis Contest.
  • Palestrante: Prof. Andrew B. Kahng (University of California at San Diego, USA)
  • Resumo: This two-part class covers issues that physical design researchers must comprehend in order to be successful in research, and to make an impact with their work. In Part I, I will discuss research mindsets, “patterns” and platforms. Some aspects include: (i) avoiding incrementality in the guise of novelty, (ii) establishing research enablements (libraries, flows, designs, etc.) and figures of merit that can adequately support claims of relevance and value, and (iii) methodology for validation and reporting.In Part II, I will discuss the role of machine learning techniques in IC physical design, as the industry addresses severe schedule, resource and quality-of-results challenges in today’s late-CMOS era. Opportunities and value propositions for data mining, machine learning, and deep learning in physical design abound. Some examples include: (i) achieving faster design convergence through new predictors of downstream flow outcomes, (ii) removing unnecessary design and modeling margins through new correlation mechanisms, and even (iii) optimizing the usage of EDA tool licenses and available schedule.
  • Bio: Andrew B. Kahng is Professor of CSE and ECE at UC San Diego, where he holds the endowed chair in High-Performance Computing. He has served as visiting scientist at Cadence (1995-1997) and as founder/CTO at Blaze DFM (2004-2006). He is the coauthor of 3 books and over 400 journal and conference papers, holds 33 issued U.S. patents, and is a fellow of ACM and IEEE. He has served as general chair of DAC, ISQED, ISPD and other conferences. His research interests include IC physical design and performance analysis, the IC design-manufacturing interface, combinatorial algorithms and optimization, and the roadmapping of systems and technology.

Friday - Aug 4
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  • Palestrante: Dr. Patrick Groeneveld (Formally Synopsys, USA)
  • Resumo: IC design is one of the best automated synthesis methodologies in all of engineering. It crosses several levels of abstraction: from logic, to net list, to placed objects and eventually ending up in a mask pattern. Unlike other disciplines such as mechanical design, this flow is truly 'push-button'. The software flow for that consists of dozens of algorithmic steps that gradually transform the design, each time predicting and correcting the major quality objectives. Though individual algorithms are relevant, it is the intricate tuning of the interaction between the steps that makes of breaks a flow. This presentation will especially address the anatomy of a good flow, and what are good strategies for successful design closure. We will provide a broad overview and reason about the global trade-offs that make the flow robust and efficient. A greedy algorithm will be presented that serves as a workhorse to top multi-objective optimization. Where most algorithms address a single objective, this method can simultaneously trade-off multiple objectives such as critical path timing, area, and leakage power.
  • Bio: Patrick Groeneveld was Chief Technologist at Magma Design Automation since its inception. He designed the revolutionary RTL to GDS2 flow which is based on a unique common data model. It combined a native sign-off STA tool that drives various logical and physical synthesis tools. After acquisition by Synopsys he worked on optimization in Design Compiler. Patrick was chair of DAC and was full professor in EE at Eindhoven University. He holds a Ph.D. in EE from Delft University of Technology. In his spare time he enjoys flying, opera, his family and absorbing useless information.
  • Palestrante: Dr. Patrick Groeneveld (Formally Synopsys, USA)
  • Resumo: IC design is one of the best automated synthesis methodologies in all of engineering. It crosses several levels of abstraction: from logic, to net list, to placed objects and eventually ending up in a mask pattern. Unlike other disciplines such as mechanical design, this flow is truly 'push-button'. The software flow for that consists of dozens of algorithmic steps that gradually transform the design, each time predicting and correcting the major quality objectives. Though individual algorithms are relevant, it is the intricate tuning of the interaction between the steps that makes of breaks a flow. This presentation will especially address the anatomy of a good flow, and what are good strategies for successful design closure. We will provide a broad overview and reason about the global trade-offs that make the flow robust and efficient. A greedy algorithm will be presented that serves as a workhorse to top multi-objective optimization. Where most algorithms address a single objective, this method can simultaneously trade-off multiple objectives such as critical path timing, area, and leakage power.
  • Bio: Patrick Groeneveld was Chief Technologist at Magma Design Automation since its inception. He designed the revolutionary RTL to GDS2 flow which is based on a unique common data model. It combined a native sign-off STA tool that drives various logical and physical synthesis tools. After acquisition by Synopsys he worked on optimization in Design Compiler. Patrick was chair of DAC and was full professor in EE at Eindhoven University. He holds a Ph.D. in EE from Delft University of Technology. In his spare time he enjoys flying, opera, his family and absorbing useless information.
  • Palestrante: Prof. Ricardo Reis (UFRGS)
  • Resumo: Most of the circuits designed nowadays use much more transistors than it is needed. The increasing leakage power and routing issues are an important reason to optimize the number of transistors, as leakage power is related to the amount of transistors. Also, the replacement of a set of basic gates by a complex gate reduces the number of connections to be implemented using metal layers as well the number of vias. The reduction of the number of connections to be implemented using metal layers helps to improve routing and also helps to improve reliability. To cope with this goal, it is needed to provide tools to automatically generate the layout of any transistor network.
  • Bio: Ricardo Reis received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Doctor Honoris Causa by the University of Montpellier in 2016. Since 1981, he is a professor at the Informatics Institute of Federal University of Rio Grande do Sul, and a leader of the Microelectronics Group. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 500 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011), representing R9. He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011 and 2012, and R9 Chapter of The Year 2013, 2014, 2016 and 2017. He is a founder of several conferences like SBCCI (sponsored by CASS in Brazil) and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. He also started with the EMicro, an annually microelectronics school in South Brazil, that now is co-sponsored by IEEE CAS chapter. In 2002 he received the Researcher of the Year Award in the state of Rio Grande do Sul. Ricardo also participates in many Latin-American research activities. Prof. Reis is a member of the IEEE since 1981 and senior member since 2006. He is also member of the ACM, founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society). The main research topics are physical design automation, circuits tolerant to radiation effects, IC design methodologies, low power design and microprocessors architecture.
  • Palestrante: Prof. Marcelo Johann (UFRGS)
  • Resumo: In this talk, we will present the effective optimization flow developed at UFRGS for the problem of cell selection from a library considering size and threshold voltage alternatives, with the goal of minimizing leakage power. Our method employs a Lagrangian Relaxation formulation with Gradient Descent updates and KKT flow conditions, which have optimality and efficiency properties of continuous functions, and are used as powerful heuristics for the discrete case of cell selection. A set of greedy and heuristic methods are used to find the best solution for each relaxed subproblem, for updating Lagrange multipliers and estimating the impact of each cell change with high timing accuracy. Both industry and academia recognized that this problem had a large room for improvement, and significant improvements have been shown in the last five years motivated by the realization of research contests in the ISPD symposium. The flow presented in this talk not only won the contest of 2013 but produced the best results for every test case shortly after, demonstrating clear superiority. We will also address other strategic and operational aspects of participating in research contests taken from the experience of the group, that achieved four times 1st and 2nd positions in the years from 2012 to 2015 with gate sizing and incremental timing-driven placement problems.
  • Bio: Marcelo de Oliveira Johann (Member of IEEE, AES, ICMA, SBC) received his Bachelor (5-years), Masters and the Ph.D. degrees in Computer Science from the Federal University of Rio Grande do Sul (UFRGS), at Porto Alegre, Brazil, in 1992, 1994 and 2001, respectively, having spent 6 months as a visiting student at UCLA, USA, in 1997. He worked as a professor at the Catholic University of Rio Grande do Sul (PUCRS) from 2000 to 2002, and is a full-time professor at UFRGS since 2003. Dr. Johann co-authored 9 book chapters and published more than 60 conference and journal papers mainly in topics related to Electronic Design Automation. His research interests include algorithms for placement, routing, discrete gate sizing, combinatorial optimization, circuits for audio, recording classical music and computer music.
  • Palestrante: Prof. Patrick H. Madden (State University of New York at Binghamton, USA)
  • Resumo: Following global placement, a circuit must be legalized, and then detail placement is performed. The algorithmic approaches used at the small scale are frequently combinatorial in nature — branch-and-bound, dynamic programming, and in some cases, greedy algorithms. In this talk, we will cover advanced applications of dynamic programming to legalization, detailed placement, and also touch on gate sizing problems. Window-based branch-and-bound methods will be presented, along with simple greedy algorithms that are surprisingly effective for mixed-size placement legalization.The talk will then consider current work on combinatorial optimization, using a novel hybrid of enumeration, greedy tree pruning, and fast multi-dimensional Pareto front algorithms. The goal of the current work is to develop an extensible general purpose combinatorial solver, allowing a unification of different physical design subproblems (e.g., detailed placement and gate sizing) into a single step.
  • Bio: Patrick H. Madden is an associate professor of computer science at Binghamton University, he received a PhD in computer science from UCLA in 1998. His research focus has been on VLSI physical design automation, with an emphasis on placement and routing. Over the past few years, his focus has shifted to general purpose combinatorial optimization, expanding from design automation into biotech areas. He is an active in the ACM, chairing ACM/SIGDA, the ACM SIG Governing Board. He has served on the program committees and steering committees of all the major design automation conferences. In addition to his research and teaching activities, he also develops apps for mobile devices, and is a mediocre guitarist.

Link for Schedule (PDF)


LOCATION

Universidade Federal do Rio Grande do Sul - Instituto de Informática
Anfiteatro do Centro de Eventos, prédio 43413 (antigo 67)
Campus do Vale, Porto Alegre - Rio Grande do Sul, Brazil.

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