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Logic Circuit Synthesis Lab |
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LogiCS Labs provide research activities in computing models and algorithms related to digital integrated circuit design flow optimization in terms of performance, power consumption, silicon area and noise immunity, at different deisgn levels: logical (technology mapping), electrical (transistor network) and physical (layout). ASIC design is also included in the team tasks as a way to verify and validate the proposed CAD tools and methods. It is registered as a Research Group at CNPq, with the name "Ferramentas Computacionais para Projeto de Circuitos e Sistemas Integrados" (in Portuguese). It also aggregates the activites of the Nangate-UFRGS Research Lab, in the scope of this R&D agreement.
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