Projects related to the Nangate-UFRGS Research Lab :

1) Physical synthesis: Circuit design is normally divided into logic synthesis and physical design. Physical synthesis merges this two steps to preserve the gains obtained by both. This research task aims the extension of physical synthesis to incorporate the flexibility of automatic cell generation.

2) Technology mapping: The step of circuit synthesis in which the building blocks that will be used in the final circuit implementation are chosen is commonly known as technology mapping. Our research goal is to extend the concept of technology mapping beyond the concept of cell library to perform technology mapping at the switch level, mapping directly to transistor networks.

3) BDD package: Many Boolean operations to be performed will need specific support. These include several tasks related to transistor level implementations. For this, we are developing a new BDD package with specific support at the switch level.

4) Logic Cell Leakage Modeling and Design Technique: Leakage current is becoming more important in logic cell power dissipation when sub-micrometer processes are targeted. Among different leakage mechanisms, sub-threshold current and gate oxide tunneling represent the main contributors. Thus, such leakage current sources should be well modeled and quantified in logic gates mainly for standard-cell based designs. Many works have been presented in literature to reduce the leakage dissipation in logic cells. Design techniques for CMOS gate leakage savings must be investigated.

5) Logic Cell Delay and Power Analytical Modeling: Analytical modeling of single CMOS gate behavior is interesting to fast estimation of delay and power consumption of digital circuits. Estimation tools are usually adopted during the design cycle instead of more accurate but more time-expensive electrical simulations. A great number of different inverter models is presented in literature. The current practice is to extend these models to more complex gates through series-parallel equivalent electrical conversion. More investigation must be done to explore such a kind of modeling in non-series-parallel transistor networks.


6) Logic Cell Layout Techniques: Layout building of logic cells is being investigated in terms of parasitic elements (contact and diffusion resistances, wire capacitances, isolation by gate and active area, and so on), since their influence in the electrical behavior of a cell tends to become more significant for sub-micrometer processes. Moreover, different CMOS logic styles require different layout strategies in order to obtain a more compact physical implementation considering, e.g., a fixed cell height (library compatibility), wire levels for routing, Euler paths, and other constraints. CAD tools for automatic layout generation are developed taking into account the results from handcraft layouts.

7) Different CMOS Logic Styles for Compatible Standard Cell Library: Different CMOS logic styles, other than conventional series-parallel gates, like mux-based cells, PTL and buffered gates, can provide improvements in terms of electrical behavior and/or layout generation when compared to standard CMOS gates. Layout compatibility is also an important factor for cell libraries built with different CMOS design styles. The same consideration should be done for latch and flip-flop construction, since a great number of topologies for memory elements has been proposed in literature and should be investigated for specific applications and requirements.

8) ASIC Design Evaluation: How to estimate the efficiency of an ASIC design generation? How estimate the impact and efficiency of different cell libraries and technology mapping procedures in the final circuit layout? These questions should be answered to provide CAD tools that reduce the gap between standard cell and full custom designs, in terms of physical area and electrical behavior. ASIC design evaluation criteria must be defined and CAD tools developed to provide and cope with such analysis.

9) Test and Validation of CMOS Cell Library: The standard cell methodology is strongly preferred for ASIC design. Cell libraries are applied to such design approach, and usually consist of hundred cells. The experimental characterization and validation of cell libraries is an imperative task. In the case of on-the-fly cell generation required by library-free technology mapping, test circuits must be also automatically provided taking into account the logic cells applied in a target specific design.

10) Visualization Interfaces: Many tasks performed by our tools exploit a new space of solution obtained by the extension of current tools to the switch level. This way, visualization interfaces are necessary to provide the user with visual insights on the relationship between logic, switch networks and layout.

11) Software Engineering and Design Databases: No design flow exists without a tight integration of tools that compose the design flow. Two main aspects of this integration are the software engineering of the flow and the use of design databases accepted by the industry. This aspect of our research focus on achieving this level of integration.