Transistor Count Optimization in IG FinFET Network Design
Vinicius N. Possani, Andre I. Reis, Renato P. Ribas, Felipe S. Marques, Leomar Soares da Rosa Jr.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.PP, no.99, 2016.

SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC
Vinicius Dal Bem, Felipe S. Marranghello, Andre I. Reis, Renato P. Ribas
IEEE Transactions on Emerging Topics in Computing, vol.PP, no.99, 2016.

Graph-Based Transistor Network Generation Method for Supergate Design
Vinicius N. Possani, Vinicius Callegaro, André I. Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, no.2, Mar. 2015. pp.692-705

Factored Forms for Memristive Material Implication Stateful Logic
Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André I. Reis, Renato P. Ribas
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol.5, no.2, June 2015. pp.267-278

Exploring the use of approximate TMR to mask transient faults in logic with low area overhead
Iuri A. C. Gomes, Mayler G. A. Martins, André I. Reis, Fernanda Lima Kastensmidt
Microelectronics Reliability, vol. 55, no.9-11, Aug.-Set. 2015. pp.2072-2076

BTI, HCI and TDDB aging impact in flip–flops
Cícero Nunes, Paulo F. Butzen, André I. Reis, Renato P. Ribas
Microelectronics Reliability, vol. 53, no.9-11, Set.-Nov. 2013. pp.1355-1359

BTI and HCI first-order aging estimation for early use in standard cell technology mapping
Paulo F. Butzen, Vinicius Dal Bem, André I. Reis, Renato P. Ribas
Microelectronics Reliability, vol. 53, no.9-11, Set.-Nov.2013. pp.1360–1364

Design of CMOS logic gates with enhanced robustness against aging degradation
Paulo F. Butzen, Vinicius Dal Bem, André I. Reis, Renato P. Ribas
Microelectronics Reliability, vol.52, no.9-10, Set.-Oct. 2012. pp.1822-1826

Contributions to the evaluation of ensembles of combinational logic gates
Renato P. Ribas, Simone Bavaresco, Nívea Schuch, Vinicius Callegaro, Marcelo Lubaszewski, André I. Reis
Microelectronics Journal, vo.42, no.2, Feb. 2011. pp.371-381

Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits
Paulo F. Butzen, Vinicius Dal Bem, André I. Reis, Renato P. Ribas
Journal of Low Power Electronics, vol.6, no.1, Apr. 2010. pp.192-200

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits
Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, André I. Reis, Renato P. Ribas
Microelectronics Journal, vol.41, no.4, Apr. 2010. pp.247-255

Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology
Digeorgia da Silva, André I. Reis, Renato P. Ribas
Microelectronics Reliability, vol.50, no.9-11, Set.-Nov. 2010. pp.1223-1229

Transistor network restructuring against NBTI degradation
Paulo F. Butzen, Vinicius Dal Bem, André I. Reis, Renato P. Ribas
Microelectronics Reliability, vol.50, no.9-11, Set.-Nov. 2010. pp.1298-1303

CMOS logic gate performance variability related to transistor network arrangements
Digeorgia da Silva, André I. Reis, Renato P. Ribas
Microelectronics Reliability, vol.49, no.9-11, Set.-Nov. 2009. pp.977-981