Simple Flow

 

 

 

 

 

 

Simple Flow is a logic synthesis tool intended to provide a front-end environment addressing simplified versions of synthesis tasks. This current release is based on a synthesis approach targeting a minimal logic network comprised only of simple cells (NAND2, NOR2, XOR2, XNOR2 and inverters). Please, refer to [1] and [2] for additional information regarding this approach.

Commands

This current release relies on the following commands:

Basic Commands

  • help - ​Prints out a welcome message and a list of commands currently available on Simple Flow. Also, this command can be used to print a help message for any implemented command, by running 'help CMD'.​ This same help message can be printed out by running 'CMD -h'.
  • summary - Prints out information about the current data structure. It is possible to specify the name related to the data structure to be printed.
  • exit - Exits from Simple Flow.

I/O Commands

  • read - Reads input files to corresponding data structure. The input files currently recognized are: '.aag', '.aig' (See [3]), and '.xaag'.
  • write - Writes output files from corresponding data structure. The output files currently recognized are: '.aag', '.aig' (See [3]), '.xaag', and '.dot' (See [4]).

Synthesis Commands

  • generate_xaig - Transforms an AIG into an XAIG. See [1] and [2].
  • min_xtors_simple_cells - Transforms an AIG (or an XAIG) into a circuit using only simple cells. See [1] and [2].
  • limit_fanout - Limits the fanout of a all cells in a circuit, given fanout limits. See [1] and [2].

Releases

simple-flow_v1 (download here) 
  • First release of Simple Flow Synthesis Tool
  • x86_64-linux-gnu only (for now)

Citation

In papers and reports, please refer to Simple Flow as follows:
LogiCS Research Labs, "Simple Flow", Release YYYYMMDD, Available in http://www.inf.ufrgs.br/logics/downloads/

In the above citation, substitute YYYYMMDD by the release version used, abbreviated as YYYY[year]MM[month]DD[day].

Contribute to Simple Flow

Simple Flow is an ongoing tool. If you want to contribute to this project, please contact us through the mail address This email address is being protected from spambots. You need JavaScript enabled to view it.

References

[1] Jody Maick Matos, Marcus Ritt, Renato P. Ribas and Andre I. Reis. "Deriving Reduced Transistor Count Circuits from AIGs". In Proc. of Symposium on Integrated Circuits and Systems Design (SBCCI), 2014. (access the paper)

[2] Jody Maick Matos, Marcos H. Backes, Marcus Ritt, Renato P. Ribas and Andre I. Reis. "Mapping Circuits with Simple Cells from Xor-And-Inverter Graphs". In Proc. of International Workshop on Logic and Synthesis (IWLS), 2015. (This email address is being protected from spambots. You need JavaScript enabled to view it.)

[3] AIGER format, developed by Armin Biere. http://fmv.jku.at/aiger/

[4] DOT format, from graph visualization package (GraphViz). http://www.graphviz.org/