Nangate A/S



Activities related to the Nangate-UFRGS Research Lab:

Lab 214
1) Physical synthesis and transistor network: Circuit design is normally divided into logic synthesis and physical design. Physical synthesis merges this two steps to preserve the gains obtained by both. This research task aims the extension of physical synthesis to incorporate the flexibility of automatic cell generation. Different methods of switch (transistor) networks are investigated.

2) Technology mapping: The step of circuit synthesis in which the building blocks that will be used in the final circuit implementation are chosen is commonly known as technology mapping. Our research goal is to extend the concept of technology mapping beyond the concept of cell library to perform technology mapping at the switch level, mapping directly to transistor networks.

3) Delay and Power Modeling: Analytical modeling of single CMOS gate behavior is interesting to fast estimation of delay and power consumption of digital circuits. Estimation tools are usually adopted during the design cycle instead of more accurate but more time-expensive electrical simulations. A great number of different inverter models is presented in the literature. The current practice is to extend these models to more complex gates through series-parallel equivalent electrical conversion. More investigation must be done to explore such a kind of modeling in non-series-parallel transistor networks.

4) Logic Cell Layout Techniques: Layout building of logic cells is being investigated in terms of parasitic elements (contact and diffusion resistances, wire capacitances, isolation by gate and active area, and so on), since their influence in the electrical behavior of a cell tends to become more significant for sub-micrometer processes. Moreover, different CMOS logic styles require different layout strategies in order to obtain a more compact physical implementation considering, e.g., a fixed cell height (library compatibility), wire levels for routing, Euler paths, and other constraints.

5) Different CMOS Logic Styles for Compatible Standard Cell Library: Different CMOS logic styles, other than conventional series-parallel gates, like mux-based cells, PTL and buffered gates, can provide improvements in terms of electrical behavior and/or layout generation when compared to standard CMOS gates. Layout compatibility is also an important factor for cell libraries built with different CMOS design styles.

6) Test and Validation of CMOS Cell Library: The standard cell methodology is strongly preferred for ASIC design. Cell libraries are applied to such design approach, and usually consist of hundred cells. The experimental characterization and validation of cell libraries is an imperative task. In the case of on-the-fly cell generation required by library-free technology mapping, test circuits must be also automatically provided taking into account the logic cells applied in a target specific design.