Dissertação de João Paulo Cardoso de Lima

Aluno: João Paulo Cardoso de Lima
Orientador: Prof. Dr. Luigi Carro

Título: PIM-gem5: a system simulator for Processing-in-Memory design space exploration
Linha de Pesquisa: Sistemas Embarcados

Data: 20/02/2019
Hora: 09h30min.
Local: AUD – 1 (Auditório 1), Prédio 43412 do Instituto de Informática da UFRGS

Banca Examinadora:
Prof. Dr. Philippe Olivier Alexandre Navaux (UFRGS)
Prof. Dr. Gabriel Luca Nazar (UFRGS)
Prof. Dr. Raimundo da Silva Barreto (UFAM – por videoconferência)

Presidente da Banca: Prof. Dr. Luigi Carro

Abstract: Processing-in-Memory (PIM) has been recently revisited to address the issues of memory and power wall, mainly due to the maturity of 3D-stacking manufacturing technology and the increasing demand for bandwidth and parallel access in emerging data-centric applications. Recent studies have shown a wide variety of processing mechanisms to be placed in the logic layer of 3D-stacked memories, not to mention the already available 3D-stacked DRAMs, such as Micron’s Hybrid Memory Cube (HMC). Most of the studies in PIM architectures use the HMC as target memory, since its logic layer is suitable for placing processing logic in the memory device. Nevertheless, the lack of tools for rapid prototyping can be a limiting factor to explore new architectures, mainly when computer architectures aim to simulate system integration. In this document, we present a PIM support for the broadly adopted gem5 simulator and a methodology for prototyping PIM accelerators. Using the proposed simulator, computer architects can model a full environment and address open problems in the PIM research field. Also, we present two case studies of a fixed-function and a programmable logic PIM placed alongside each vault controller, and we highlight the generic points of our implementation which can be used to the exploit efficiency of new PIM accelerators.

Keywords: Processing-in-memory, system simulator, 3D-stacked memories.