Proposta de Tese de Augusto Neutzling Silva

Aluno: Augusto Neutzling Silva
Orientador: Prof. Dr. Renato Perez Ribas

Título: Logic Synthesis for Emerging Nanotechnologies

Linha de Pesquisa: Microeletrônica

Data: 11/08/2017
Horário: 09h30min
Local: Prédio 43412 – Sala 215, Instituto de Informática

Banca Examinadora:
Prof. Dr. Marcelo de Oliveira Johann (UFRGS)
Prof. Dr. Felipe de Souza Marques (UFPel)
Prof. Dr. Ricardo dos Santos Ferreira (UFV – por videoconferência)

Presidente da Banca: Prof. Dr. Renato Perez Ribas

Abstract: Threshold logic is a powerful alternative paradigm for realizing Boolean functions in digital designs. A threshold logic function (TLF) can be roughly defined as a Boolean function in which the output is evaluated in terms of input weights and a threshold value. Although the subject has been theoretically studied since the 1960’s, the lack of effective hardware implementation for threshold functions led to a loss of interest in developing a threshold logic design flow. However, for some of the emerging technologies, such as memristors, spintronic, quantum cellular automata (QCA) and resonant tunneling devices (RTD), such a logic design strategy seems to be more appropriate than the traditional switch-based CMOS circuitry. Thus, research and development of synthesis and verification methods applicable to large, multi-level threshold circuits are desired. Existing state-of-the-art threshold logic synthesis tools rely on locally resynthesizing each single-output node out of circuits initially mapped disregarding thresholdness. This work presents the first effective technology mapping approach for threshold logic gates (TLGs), which is based on identifying threshold logic functions during the mapping. This enables us to explore the entire circuit-level search space, seeking a threshold logic covering. As a consequence, we improve both area and delay results, as well as the synthesis scalability. A second contribution introduced in this thesis improves the quality of results by efficiently exploring redundant cuts. The technology mapper we propose herein is also able to target different threshold-based area estimations: the total summation of input weights and threshold values; the total summation of gate inputs; or the total number of TLGs. Finally, we propose a TLF-based approach to perform logic synthesis for majority-gate-based emerging nanotechnologies.

Keywords: Digital Circuits; Logic Synthesis; Technology mapping; Nanotechnologies; Threshold Logic; Majority Gates.