Tese de Doutorado de Calebe Micael de Oliveira Conceição

Aluno: Calebe Micael de Oliveira Conceição
Orientador: Prof. Dr. Ricardo Augusto da Luz Reis

Título: Minimizing Transistor Count in Transistor Networks
Linha de Pesquisa: Ferramentas para Automação de Projeto Eletrônico

Data: 18/10/2019
Horário: 14h45min.
Local: AUD-1 (Auditório 1) no prédio 43412 do Instituto de Informática da UFRGS.

Banca Examinadora:
Prof. Dr. Felipe de Souza Marques (UFPel – por videoconferência)
Prof. Dr. Marcelo de Oliveira Johann (UFRGS)
Prof. Dr. Ricardo Pezzuol Jacobi (UNB – por videoconferência)

Presidente da Banca: Prof. Dr. Ricardo Augusto da Luz Reis

Abstract: The evolution of Integrated Circuits Technology demands optimization of IC design. Nowadays, many circuits use much more transistors than necessary as a broad set of ASICs use a library of pre-designed cells. The small number of logic functions that a traditional cell library provides represents an inherent limitation in the optimization of the number of transistors in the circuit. This limitation directly influences the circuit performance. A library free design approach is necessary to obtain optimized circuits, using tools to allow the layout synthesis of any transistor network. The goal of this thesis is to develop a method to optimize the logical netlist of a circuit willing to reduce the number of transistors, connections, and vias. The optimized netlist serves as input to the layout synthesis tool. We post-process the original netlist generated in the traditional standard cell design flow systematically, replacing sets of cells by one new gate of equivalent logic generated on demand to reduce the number of transistors. We merge groups of connected combinational cells of unitary fanout into a new complex gate that is, in general, not available in the traditional cell library. The new gate has a custom transistor network that can be appropriately arranged and sized to fit the specific requirements of where it is located in the circuit. The experiments performed so far shows that our method allows about 13% of reduction of the number of transistors in the entire circuit in comparison to netlists generated using other logic minimization tools. We also reduce the number of instances, pins and connections in the experiments we performed in 14%, 11% and 10% on average, respectively, when compared to the netlist generated with a leading academic logic synthesis tool. We also investigate the impact of the proposed optimization in area and wirelength, achieving an estimated average reduction of 5% in the area and up to 14% reduction in total wirelength. These results evidence the optimization opportunities neglected in standard cell design approach and show the advantages of library free synthesis.

Keywords: EDA. Logic Synthesis. Library free. Cell clustering. Transistor network. Transistor count. Microelectronics.