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Tese de Marcelo Brandaleiro


Detalhes do Evento


Aluno: Marcelo Brandaleiro
Orientador: Prof. Dr. Antonio Carlos Schneider Beck Filho

Título: MuTARe: A Multi-Target, Adaptive Reconfigurable Architecture
Linha de Pesquisa: Sistemas Embarcados

Data: 28/03/2019
Horário: 14h30
Local: Evento Design Automation and Test in Europe, em Florença, na Itália.

Banca Examinadora:
– Prof. Dr. Luca Carloni (Columbia)
– Profª. Drª. Cristina Silvano (POLIMI)
– Prof. Dr. Michael Hübner (B-TU)
– Prof. Dr. Paolo Rech (UFRGS)

Presidente da Banca: Prof. Dr. Antonio Carlos Schneider Beck Filho
 

Abstract: Power consumption, earlier a design constraint only in embedded systems, has become the major driver for architectural optimizations in all domains, from the cloud to the edge. Application-specific accelerators provide a low-power processing solution by efficiently matching the hardware to the application; however, since in many domains the hardware must execute efficiently a broad range of fast-evolving applications, unpredictable at design time and each with distinct resource requirements, alternatives approaches are required. Besides that, the same hardware must also adapt the computational power at run time to the system status and workload sizes. To address these issues, this thesis presents a general-purpose reconfigurable accelerator that can be coupled to a heterogeneous set of cores and supports Dynamic Voltage and Frequency Scaling (DVFS), synergistically combining the techniques for a better match between different applications and hardware when compared to current designs. The resulting architecture, MuTARe, provides a coarse-grained regular and reconfigurable structure which is suitable for automatic acceleration of deployed code through dynamic binary translation. In extension to that, the structure of MuTARe is further leveraged to apply two emerging computing paradigms that can boost the power-efficiency: Near-Threshold Voltage (NTV) computing (while still supporting transparent acceleration) and Approximate Computing (AxC). Compared to a traditional heterogeneous system with DVFS support, the base MuTARe architecture can automatically improve the execution time by up to 1.3×, or adapt to the same task deadline with 1.6× smaller energy consumption, or adapt to the same low energy budget with 2.3× better performance. In NTV mode, MuTARe can transparently save further 30% energy in memory-intensive workloads by operating the combinatorial datapath at half the memory frequency. In AxC mode, MuTARe can further improve power savings by up to 50% by leveraging approximate functional units for arithmetic computations.

Keywords: Computer architecture. reconfigurable architecture. adaptable architecture. approximate computing. near-threshold voltage computing.