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Research Groups | Test and Design for Testability of Hardware and Software Integrated Systems Group

Research in this group aims at designing easily testable, reliable, and affordable integrated systems. Issues related to the off-line and online testing of complex integrated systems are considered. The target systems include digital and analog circuits, programmable devices (FPGAs and FPAAs), systems integrated in a single chip (SoCs) and intra-chip networks (NoCs).
Researchers


Research Themes

  • Tools for analysis and injection of faults in integrated circuits: automation of the fault injection process for reliability analysis of integrated circuits.
  • Modeling of transient faults in integrated circuits: definition and validation of realistic fault models for nanoscale systems.
  • Protection of encryption hardware against attacks: definition, implementation, and evaluation of hardware-based protection methods against malicious attacks in encryption circuits (smartcards, etc.).
  • Test of integrated systems based on hardware reuse: tools for test planning for integrated systems (based on hardware components) aiming low cost test.
  • Intra-chip network test: definition of fault models, development and implementation of test techniques for intra-chip networks (NoCs).
  • Self-checking and fault tolerant integrated systems: design for reliability, security and fault tolerance of integrated circuits and systems, including automation systems. Planning of test and monitoring strategies for predictive and intelligent maintenance.
  • Test of analog and mixed-signal systems and micro systems: development of methods for test planning and architectures for test of analog and mixed-signal circuits (analog-digital, micro-electro-mechanical, etc.).
  • Reliability of systems based on programmable devices: reliability analysis of analog and digital programmable devices, given the new fault models arising from nanoscale technologies. Definition of protection and fault tolerance techniques for those devices.

Recent Research Projects in the Field

  • HardTeste – Design for test and fault tolerance of hardware systems:  definition of solutions for design for off-line and online test and for fault tolerance of heterogeneous integrated systems (digital, analog, and mixed).  (2004-2007). UFRGS. Funding: CNPq.
  • Intelligent Maintenance Reference Center: runtime monitoring applied to predictive and intelligent maintenance. Started in 2006. UFRGS and SENAI Nacional. Funding: SENAI.
  • SEEP – Platform based electronic embedded systems: test of hardware platforms for embedded systems through component reuse (processors, intra-chip network). (2003-2007). UFRGS. Funding: CNPq.
  • SOC-MICRO: test of programmable analog circuits. (2003-2007). Funding: CNPq.
  • CAPES-COFECUB – Use of intra-chip networks in SoCs (NoCs): Design, Reconfigurability and Test: test of integrated systems based on intra-chip networks. (2006-2007). Funding: CAPES (Brazil) and COFECUB (France).
  • NAMITEC – Nanoelectronics technology for intelligent integrated systems: design for test and fault tolerance of hardware systems:  Test of mixed systems, test of integrated systems, and test based on intra-chip networks. Started in 2005. UFRGS. Funding: CNPq and MCT.


Recent Research Results

  • Test and diagnostics of the CPU board of a programmable logic controller – Altus S.A.;
  • Design of a fault tolerant routing matrix – Siemens of Brazil;
  • Design of a self-testing core for the 8051 microcontroller – CPqD.