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Tese de Anderson Luiz Sartor

Detalhes do Evento

Aluno: Anderson Luiz Sartor
Orientador: Prof. Dr. Antônio Carlos Schneider Beck Filho
Título: Adaptive and Polymorphic VLIW Processor to Dynamically Balance Performance, Energy Consumption, and Fault Tolerance
Linha de Pesquisa: Sistemas Embarcados

Data: 09/03/2018
Horário: 13h30min.
Local: Auditório Prof. Castilho do Prédio 43424 do Instituto de Informática.

Banca Examinadora:
Prof. Dr. Gabriel Luca Nazar (UFRGS)
Profa. Dra. Monica Magalhães Pereira (UFRN – por videoconferência)
Prof. Dr. Alexandre de Morais Amory (PUCRS)

Presidente da Banca: Prof. Dr. Antônio Carlos Schneider Beck Filho

Abstract: Performance is no longer the only optimization goal when designing a new processor. Reducing energy consumption is also mandatory: while most of the embedded devices are heavily dependent on battery power, General-Purpose Processors (GPPs) are being pulled back by the limits of Thermal Design Power (TDP).  Moreover, due to technology scaling, soft error rate (i.e., transient faults) has been increasing in modern processors, which affects the reliability of both space and ground-level systems. In addition, most traditional homogeneous and heterogeneous processors have a fixed design, which limits its runtime adaptability. Therefore, they are not able to cope with the changing application behavior when one considers the axes of fault tolerance, performance, and energy consumption altogether. In this context, we propose two processor designs that are able to trade-off these three axes according to the application at hand and system requirements. Both designs rely on an instruction duplication with rollback mechanism that can detect and correct errors and a power gating module to reduce the energy consumption of the functional units. The former design, called adaptive processor, uses thresholds defined at design time to allow runtime adaptation of the application’s execution and controls the application’s Instruction-Level Parallelism (ILP) to create more slots for duplication or power gating. The latter design (polymorphic processor) takes the former one step further by dynamically reconfiguring the hardware and evaluating different processor configurations for each application, and it also exploits the available pipelanes to maximize the number of applications that are executed concurrently. Moreover, a hybrid fault injector was also developed to speed up the fault injection campaign while maintaining gate-level accuracy. For the adaptive processor using an energy-oriented configuration, it is possible, on average, to reduce energy consumption by 37.2% with an overhead of only 8.2% in performance, while maintaining low levels of failure rate, when compared to a fault-tolerant design. For the polymorphic processor, results show that the dynamic reconfiguration of the processor is able to efficiently match the hardware to the behavior of the application, according to the requirements of the designer, which would not be possible to achieve with its static counterpart.
Keywords: Adaptive Processor, Fault Tolerance, Energy Consumption, Performance, VLIW.