Português English
Contato

Tese de Felipe Martin Sampaio


Detalhes do Evento


Aluno: Felipe Martin Sampaio
Orientador: Prof. Dr. Sergio Bampi
Coorientador: Prof. Dr. Bruno Zatt (UFPel)

Título: Energy-Efficient Memory Architecture Design and Management for Parallel Video Coding
Linha de Pesquisa: Arquitetura e Projeto de Sistemas Computacionais

Data: 12/03/2018
Horário: 13h
Local: Prédio 43412 – Sala 215 (sala de videoconferência), Instituto de Informática

Banca Examinadora:
Prof. Dr. Andre Inacio Reis (UFRGS)
Prof. Dr. Marcelo Schiavon Porto (UFPel – por videoconferência)
Prof. Dr. Nikil Devdas Dutt (Univ. of California – Irvine – por videoconferência)

Presidente da Banca: Prof. Dr. Sergio Bampi

Abstract: This Thesis presents the design of an energy-efficient hybrid scratchpad video memory architecture (called Hy-SVM) for parallel HEVC. Video coding stands out as a high complex part in the video processing applications. HEVC standard brings innovations that hardly complicate the memory requirements, mainly due to: (a) the novel coding structures, which aggravates the computational complexity by providing a wider range of possibilities to be analyzed; and (b) the high-level parallelism features provided by the Tiles partitioning, which provides performance acceleration, but, at the same time, strongly adds hard challenges to the memory infrastructure. The main bottleneck in terms of external memory transmission and on-chip storage is the reference frames data: which consists of already coded (and reconstructed) entire frames that must be stored and intensively accessed during the encoding process of future frames. Due to the large volume of data required to represent the reference frames, they are typically stored in the external memory (especially when high-definition videos are targeted). The proposed Hy-SVM architecture is inserted in a video coding system, which is based on multiple Tiles partitioning to enable parallel HEVC encoding: each Tile is assigned to a specific processing unit. The key ideas of Hy-SVM include: application-specific design and management; combined multiple levels of private and shared memories that jointly exploits intra-Tile and inter-Tiles data reuse; scratchpad memories (SPMs) as energy-efficient on-chip data storage; combined SRAM and STT-RAM hybrid memory (HyM) design. We propose a design methodology for Hy-SVM that leverages application-specific properties to properly define the HyMs parameters. In order to provide run-time adaptation (for both off- and on-chip parts), Hy-SVM integrates a memory management layer composed of: (1) overlap prediction, which identifies the redundant memory access behavior by analyzing monitored past frames encoding to provide improved inter-Tiles data reuse exploitation; (2) memory pressure management, which aims on balancing the Tiles-accumulated memory pressure targeting on improving external memory communication channel usage; and (3) lifetime-aware data management scheme that alleviates STT-RAM SPMs of high bit-toggling write accesses to increase the cells lifetime, as well as to reduce overhead issues related to poor write characteristics of STT-RAM. Application-specific knowledge was exploited, at run time, by: inheriting HEVC properties and performing run-time monitoring of memory accesses. Such information is used to properly design the on-chip video memories, as well as being utilized as input parameters for the schemes of the memory management part. Based on the run-time decisions from the proposed Hy-SVM management strategies, Hy-SVM integrates distributed memory access management units (MAMUs) to control the access dynamics of private and shared SPMs. Additionally, adaptive power management units (APMUs) are able to strongly reduce on-chip energy consumption due to an accurate overlap prediction. The experimental results demonstrate Hy-SVM overall energy savings under several HEVC encoding scenarios. Compared to traditional data reuse schemes, like Level-C, the combined intra-Tile and inter-Tiles data reuse provides 69%-79% of energy reduction. Regarding related HEVC video memory architectures, the savings varied from 2.8% (worst case) to 67% (best case). From the external memory perspective, Hy-SVM can improve data reuse (by exploiting inter-Tiles data redundancy), resulting on 11%-71%% of reduced off-chip energy consumption. Additionally, our APMU contributes by reducing on-chip energy consumption of Hy-SVM by 56%-95%, for the evaluated HEVC scenarios. Thus, compared to related works, Hy-SVM presents the lowest on-chip energy consumption. The memory pressure management scheme can reduce the variations in the memory bandwidth by 37%-83% when compared to the traditional raster scan processing for 4- and 16-core parallelized HEVC encoder. The lifetime-aware data management significantly improves the enHyV STT-RAM lifetime, achieving 0.83 of normalized lifetime (near to the optimal case). Moreover, the overhead of implementing our management units insignificantly affects the performance- and energy-efficiency of Hy-SVM.
Keywords: High-Efficiency Video Coding. Parallel Processing. On-Chip Memory Design. Memory Management. Application-Specific Knowledge. Emerging Memory Technologies and Organizations.