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Conferences 2009 HERVE, M. ; COTA, E. ; Kastensmidt, Fernanda Lima ; LUBASZEWSKI, M.
. NoC Interconnection Functional Testing: Using
Boundary-Scan to Reduce the Overall Testing Time. In: IEEE Latin-American
Test Workshop, 2009, Buzios. Proceedings of IEEE
Latin-American Test Workshop. Los Alamitos : IEEE, 2009.
p. 1-6. Assis, T. ; KASTENSMIDT, F. L. ; WIRTH, G. ; REIS, Ricardo . Measuring the effectiveness of symmetric
and asymmetric transistor sizing for Single Event Transient mitigation in
CMOS 90nm technologies. In: 10th Latin American Test Workshop, 2009. 10th
Latin American Test Workshop. Los Alamitos : IEEE. p.
1-6. AMARAL, A. ; MARTINS, C. ; KASTENSMIDT, F. L. . Reducing reconfiguration times of FPGA-based
systems using Multi-Level Reconfiguration. In: 5th Southern Conference on
Programmable Logic, 2009. 5th Southern Conference on Programmable Logic. Los
Alamitos : IEEE, 2009. p. 217-222. HERVE, M. ; COTA, E. ; KASTENSMIDT, F. L. ; LUBASZEWSKI, M. . Diagnosis of interconnect shorts in mesh NoCs. In: 3rd ACM/IEEE International Symposium onNetworks-on-Chip, 2009, CONCATTO, C. ; CARRO, Luigi ; KASTENSMIDT, F. L. ; Susin, A. ;
KREUTZ, M. . NoC Power Optimization
Using a Reconfigurable Router. In: IEEE Computer Society Annual Symposium on
VLSI, 2009, ABATE, F. ;
STERPONE, L. ; Violante, M. ; KASTENSMIDT, F. L. . A
study of the Single Event Effects impact on functional mapping within Flash-based
FPGAs. In: Design, Automation & Test in CONCATTO, C. ; ALMEIDA, P. ; KASTENSMIDT, F. L. ; COTA, E. ;
LUBASZEWSKI, M. ; HERVE, M. . Improving
yield of torus nocs
through fault-diagnosis-and-repair of interconnect faults. In: 15th IEEE
International On-Line Testing Symposium, 2009, Sesimbra-Lisbon.
15th IEEE International On-Line Testing Symposium. Los Alamitos : IEEE, 2009. p. 61-66. AZAMBUJA, J. R. ; SOUSA, F. ; ROSA, L. ; KASTENSMIDT, F. L. . Evaluating large grain TMR and selective
partial reconfiguration for soft error mitigation in SRAM-based FPGAs. In: 15th IEEE International On-Line Testing
Symposium, 2009, Sesimbra-Lisbon. 15th IEEE
International On-Line Testing Symposium. Los Alamitos : IEEE, 2009. p. 101-106. BASTOS, R. ; MONNET, Y. ; SICARD, G. ; KASTENSMIDT, F. L. ;
RENAUDIN, M. ; REIS, Ricardo . Comparing
transient-fault effects on synchronous and on asynchronous circuits. In: 15th
IEEE International On-Line Testing Symposium, 2009, Sesimbra-Lisbon.
15th IEEE International On-Line Testing Symposium. Los Alamitos : IEEE, 2009. p. 29-34. 2008 LISBOA, C. L. ; KASTENSMIDT, F. L. ; CARRO, Luigi . Analyzing the Effect of Soft Error Rate in
the Granularity of Recomputation-based Techniques. In:
Workshop on Radiation Effects and Fault Tolerance in Nanometer Technologies, 2008,
LAZZARI, Cristiano ; Assis, T. ; KASTENSMIDT, F. L. ; WIRTH, G. ; Anghel, L. ; REIS, Ricardo . SET-Factor: An Analysis and
Design Tool to Reduce SET Sensitivity in Integrated Circuits. In: European
Test Symposium (ETS), 2008, Lago Maggiore. Proceedings of European Test Symposium (ETS), 2008. WIRTH, G. ; RIBEIRO, I. ; KASTENSMIDT, F. L. . Single Event Transients in Logic Circuits
Evidence for Load Induced Pulse Broadening. In: IEEE Nuclear and Space
Radiation Effects Conference (NSREC), 2008, LAZZARI, Cristiano ; Assis, T. ; KASTENSMIDT, F. L. ; WIRTH, G. ; REIS,
Ricardo ; Anghel, L. . An Analysis and Design
Technique to Reduce SET Sensitivity in Combinational Integrated Circuits. In:
IFIP/IEEE VLSI-SoC2008, International Conference on Very Large Scale
Integration, 2008, Assis, T. ; Kastensmidt, Fernanda Lima ; WIRTH, G. ; REIS, Ricardo
. Analysis of Single
Event Effects for Different Angles and Impact Regions at a NMOS 90 nm 3D
Device. In: DECIDE- Second International Workshop onn
Dependable Circuit Design, 2008, Playa del Carmen. DECIDE- Second
International Workshop onn Dependable Circuit
Design, 2008. WIRTH, G. ; RIBEIRO, I. ; Kastensmidt, Fernanda Lima . Single Event Transients in Logic Circuits -
Evidence for Load Induced Pulse Broadening. In: IEEE Nuclear and Space
Radiation Effects Conference (NSREC), 2008, RIBEIRO, I. ; WIRTH, G. ; Kastensmidt, Fernanda Lima . Modeling the Effects of Broadening and
Degradation of Single Event Transient Pulses in Integrated Circuits. In: 8th
European Workshop on Radiation and Its Effects on Components and Systems
RADECS, 2008, Jyvãskylã. Proceedings of 8th
European Workshop on Radiation and Its Effects on Components and Systems
RADECS. Pilotto, Conrado ; AZAMBUJA, J. R. ; KASTENSMIDT, F. L. . Synchronizing triple modular redundant
designs in dynamic partial reconfiguration applications. In: Synchronizing
triple modular redundant designs in dynamic partial reconfiguration
applications, 2008, Gramado. Proceedings of SBCCI, 2008.
p. 199-204. Balen, T. ; LEITE, F. ; Kastensmidt, Fernanda Lima ; LUBASZEWSKI,
M. . A Self-Checking
Scheme to Mitigate Single-Event Upset Effects in SRAM-based FPAAs. In: Radiation Effects on Components and Systems
Workshop, 2008, 2007 Jean Carlo Hamerski,
Everton Reckziegel, Fernanda
Lima Kastensmidt. _Evaluating Memory Sharing Data Size and TCP Connections in the
Performance of a Reconfigurable Hardware-based Architecture for TCP/IP Stack.
15th Annual IFIP International Conference on Very Large Scale
Integration, VLSI-SOC, 2007. (accepted). Egas Henes Neto, Fernanda Lima Kastensmidt and Gilson Wirth. Tbulk-BICS:
A Built-In Current Sensor Robust to Process and Temperature Variations for
SET Detection. IEEE RADECS Conference. 2007. (accepted) Carlos Arthur Lisboa, Egas Henes Neto, Fernanda Lima Kastensmidt,
Gilson Wirth, Luigi Carro. Using
Built-in Sensors to Cope with Long Duration Trnasient
Faults in Future Technologies. IEEE International Test Conference, 2007, San
Jose. Erika Cota, Fernanda Lima Kastensmidt, Maico Cassel, Paulo
Meirelles, Alexandre Amory, Marcelo Lubaszewski. Redefining and Testing Interconnect Faults in Mesh NoCs. IEEE International Test Conference, 2007, San Jose.
Egas Henes Neto, Fernanda Lima Kastensmidt
and Gilson Wirth. A Built-In Current
Sensor for High Speed Soft Errors Detection Robust to Process and Temperature
Variations. Symposium On Integrated Circuits And Systems Design (SBCCI). Lorenzo Petroli, Carlos Lisboa, Fernanda Kastensmidt and Luigi
Carro. Using Majority Logic
to Cope with Long Duration Transient Faults. Symposium On Integrated Circuits
And Systems Design (SBCCI). Arthur Pereira Frantz, Maico
Cassel, Fernanda Lima Kastensmidt, _rika Cota, Luigi Carro, Avoiding
Router Crash Faults in NoCs at Design Level. DATE
Workshop on Network on Chips. 2007. Gustavo NEUBERGER, Fernanda
Lima KASTENSMIDT, Ricardo REIS, Gilson WIRTH, Christian PACHA, Ralf
BERDERLOW. Statistical Analysis of Variability of Flip-Flop Race Immunity in
130nm and 90nm CMOS Technologies. In: Latin Test Henrique C. Freitas, Tiago R. Balen, Fernanda Lima Kastensmidt,
Marcelo S. Lubaszewski, M. Renovell.
A Self-recovering Scheme to Mitigate Single Event Upset Effects in SRAM-based
Field Programmable Analog Arrays. IEEE Computer Society Annual Symposium on
VLSI (ISVLSI), 2007. ISBN: 0-7695-2896-1 Fernanda Lima Kastensmidt.
Designs for Soft Error Testing and Diagnosis in SRAM-based FPGAs. In: Single Event Effect Symposium (SEE), 2007, 2006 WIRTH, G. I. ; VIEIRA, Michele G ; HENES NETO, Egas ;
KASTENSIMIDT, Fernanda G L . Generation
and Propagation of Single Event Transients in CMOS Circuits. In: 9th IEEE
Workshop on Design & Diagnostics of Electronics Circuits and Systems,
2006, Praga. Proceedings of the IEEE DDECS 2006. WIRTH, G. ; VIEIRA, Michele ; HENES NETO, E. C. ; KASTENSMIDT, F.
L. . Evaluating the
Sensitivity of CMOS Circuits to Single Event Transients. In: Latin Americ Test Workshop (LATW), 2006, ROLT, J. ; WIRTH, G. ; KASTENSMIDT, F. L. ;
REIS, Ricardo . Analyzing
the Effect of CMOS Process Variability on the SRAM cell. In: Latin Americ Test Workshop (LATW), 2006, HENES NETO, E. C. ; WIRTH, G. ; KASTENSMIDT,
F. L. . Using Bulk Built-In
Current Sensors to Detect Transient Faults in SRAM Memory Architectures. In:
Latin Test FRANTZ, Arthur Pereira ; KASTENSMIDT, F. L. . SEU Effects Evaluation on a NoC Router Architecture. In:
Latin Americ Test Council (LATW), 2006, NEVES, C. ; HENES NETO, E. C. ; RIBEIRO, I. ; WIRTH, G. ;
KASTENSMIDT, F. L. ; GUNTZEL, Jos_ . Automatic Evaluation of Single Event Transient Propagation
in CMOS Logic Circuits Based on Topological Timing Analysis. In: Latin
American Test Workshop (LATW), 2006, BASTOS, R. ; KASTENSMIDT, F. L. ; REIS, Ricardo . Design of a Robust 8-bit Microprocessor to
Soft Single Event Effects. In: Latin American Test Workshop (LATW), 2006, NEVES, C. ; HENES NETO, E. C. ; RIBEIRO, I. ; WIRTH, G. ;
KASTENSMIDT, F. L. ; GUNTZEL, Jos_ . Avoiding Circuit Simulation for the Analysis of
Single Event Transient Propagation in Combinational Circuits. In: European
Test Symposium (ETS), 2006, CASSEL, M. ; KASTENSMIDT, F. L. . Evaluating One-Hot Encoding Finite State
Machines for SEU Reliability in SRAM-based FPGAs. In:
International On-Line Testing Symposium (IOLTS), 2006, KASTENSMIDT, F. L. ; HENES NETO, E. C. ; CARRO, Luigi ; WIRTH, G.
. Evaluating SET
Resilience with Duplicated Routing in SRAM-based FPGAs.
In: Single Event Effect Symposium (SEE), 2006, BASTOS, R. ; KASTENSMIDT, F. L. ; REIS, Ricardo . Design at High Level of a Robust 8-Bit
Microprocessor to Soft Errors by Using Only Standard Gates. In: Symposium On
Integrated Circuits And Systems Design, 2006. Symposium On Integrated
Circuits And Systems Design (SBCCI). FRANTZ, Arthur Pereira ;
KASTENSMIDT, F. L. ; COTA, E. ; CARRO, Luigi . Evaluation of SEU and
Crosstalk Effects in Network-on-Chip Switches. In: Symposium On Integrated
Circuits And Systems Design, 2006. Symposium On Integrated Circuits And
Systems Design. FRANTZ, A. P. ;
KASTENSMIDT, F. L. ; COTA, E. ; CARRO, Luigi . Dependable Network-on-Chip
Router Able to Simultaneously Tolerate Soft Errors and Crosstalk. In:
International Test Conference, 2006, San Jose. International Test Conference
(ITC). WIRTH, G. ;
RIBEIRO, 2005 KASTENSMIDT, F. L., CARRO, Luigi,
STERPONE, L., REORDA, M. On the Optimal Design of Triple Modular Redundancy
Logic for SRAM-based FPGAs In: Design Automation
and Test in Europe (DATE), 2005, NEUBERGER, G., KASTENSMIDT, F. L., WIRTH,
G.,REIS, R. Analyzing Transient Fault Effects in the
Periphery Logic of SRAM Memories. In: IEEE Latin-American Test Workshop (6. : 2005 : WIRTH, G., VIERIA, M., KASTENSMIDT, F. L.
Computer Efficient Modeling of SRAM cell Sensitivity to SEU. In: IEEE
Latin-American Test Workshop (6. : 2005 : KINZEL, C., KASTENSMIDT, F. L., CARRO, L.
Mapping the Virtex Customization Bits with JBits Classes for Selective Bitstream
Fault Injection. IEEE Latin-American Test Workshop (6. :
2005 : NEUBERGER, Gustavo ; LIMA KASTENSMIDT, F. ; REIS, Ricardo . TOC-BISR: A Self-Repair Scheme for
Memories in Embedded Systems. In: International Embedded Systems Symposium,
2005, HENES NETO, E. C. ; VIERIA, M. ; LIMA KASTENSMIDT, F. ; WIRTH, G.
. Evaluating Fault
Coverage of Bulk Built-in Current Sensor for Soft Errors in Combinational and
Sequential Logic. In: Symposium On Integrated Circuits And Systems Design,
2005, Florian_polis. SYMPOSIUM ON INTEGRATED
CIRCUITS AND SYSTEMS DESIGN. VIERIA, M. ;
HENES NETO, E. C. ; WIRTH, G. ; KINZEL FILHO, C. ;
BASTOS, R. P., 2004 Kastensmidt, Fernanda Gusm_o de. Neuberger, Gustavo. Carro, Luigi.
Reis, Ricardo. Designing
and Testing Fault-Tolerant Techniques for SRAM-based FPGAs.
In: ACM Computer Frontiers Conference (1 : 2004 : Reis, Ricardo. Kastensmidt, Fernanda Gusm_o de. Guntzel, Jos_ Luis.
Physical Design Methodologies for Performance Predictability and
Manufacturability. In: ACM Computer Frontiers Conference (1
: 2004 : Neuberger, Gustavo. Reis, Ricardo Augusto da Luz. Kastensmidt,
Fernanda Gusm_o de Lima. Improving
the use of Reed-Solomon Codes to Increase Fault-tolerance in very deep
sub-micron integrated circuits. In: Digest of papers: 5th IEEE Latin American
Test Workshop, march 8-10, 2004 p.56-59. LIMA KASTENSMIDT, F., NEUBERGER, Gustavo,
REIS, Ricardo 2003 Kastensmidt, Fernanda Gusm_o de Lima. Carro, Luigi. Reis, Ricardo
Augusto da Luz. Designing
Single Event Upset Mitigation Techniques for SRAM-Based FPGAs.
In: IFIP WG 10.5 International Conference on Very Large Scale Integration of
System-on-Chip (2003 : Kastensmidt, Fernanda Gusm_o de Lima. Designing single event upset mitigation
techniques for large SRAM-Based FPGA components. 2003.
157 f. : il. Tese (doutorado)-Universidade Federal do Rio Grande do Sul.
Instituto de Inform_tica. Programa de P_s-Gradua?_o em Computa?_o. Porto
Alegre, BR-RS, 2003. Ori.: Reis, Ricardo Augusto da Luz. Lima, Fernanda Gusmao de. Carro, Luigi. Reis, Ricardo Augusto da
Luz. Designing Fault
Tolerant Systems into SRAM-based FPGAs [recurso eletr_nico]. In: Design
Automation Conference (40. : 2003 : Lima, Fernanda Gusmao de. Carro, Luigi. Reis, Ricardo Augusto da
Luz. Designing Fault
Tolerant Systems into SRAM-based FPGAs. In: South
Symposium on Microelectronics (18. : 2003 : Lima, Fernanda Gusmao de. Carro, Luigi. Reis, Ricardo Augusto da
Luz. Single event upset
mitigation tecniques for SRAM-based FPGAs. In: IEEE Latin-American Test Workshop (4. : 2003 : Lima, Fernanda Gusmao de. Carro, Luigi. Reis, Ricardo Augusto da
Luz. Reducing Pin and area
overhead in fault-tolerant FPGA-based designs [recurso
eletr_nico]. In: ACM/Sigda
International Symposium on Field-Programmable Gate Arrays (11. : 2003 : Neuberger, Gustavo. Lima, Fernanda Gusmao de. Carro, Luigi. Reis,
Ricardo Augusto da Luz. A
multiple bit upset tolerant SRAM memory. In: ACM transactions on design
automation of electronic systems. New York Vol. 8, No. 4
(2003), p. 577-590 : il. Neuberger, Gustavo. Lima, Fernanda Gusmao de. Carro, Luigi. Reis,
Ricardo Augusto da Luz. Evaluating
Fault Coverage of Concurrent Error Detection Techniques for Arithmetic
Circuits in SRAM-based FPGAs. In: South Symposium
on Microelectronics (18. : 2003 : Neuberger, Gustavo. Lima, Fernanda Gusmao de. Carro, Luigi. Reis,
Ricardo Augusto da Luz. A
multiple bit upset tolerant SRAM memory. In: IEEE Latin-American Test
Workshop (4. : 2003 : 2002 Hentschke, Renato Fernandes. Marques, Felipe
de Souza. Lima, Fernanda Gusmao de. Carro, Luigi.
Susin, Altamiro Amadeu. Reis, Ricardo Augusto da Luz. Analyzing area and performance penalty of
protecting different digital modules with hamming code and triple modular
redundancy. In: Symposium on Integrated Circuits and Systems Design (15. : 2002 : Lima, Fernanda Gusmao de. Lima, Fernanda Gusmao de. Carro, Luigi.
Reis, Ricardo Augusto da Luz. Analyzing SEU Mitigation Techniques for
SRAM-based FPGAs. In: South Symposium on Microelectronics (17. : 2002 :
Canela). Proceedings. Porto Alegre : Instituto de Informatica da UFRGS, 2002.
p. 51-54 : il. Lima, Fernanda Gusmao de. Carro, Luigi. Velazco, Raoul. Reis,
Ricardo Augusto da Luz. Injecting
multiple upsets in a SEU tolerant 8051 micro-controller. In: IEEE
International On-Line Testing Workshop (8. : 2002 :
Isle of Bendor). Proceedings. Los
Alamitos : IEEE Computer Society, 2002. p. 194. : il. Lima, Fernanda Gusmao de. Carro, Luigi. Velazco, Raoul. Reis,
Ricardo Augusto da Luz. Injecting
multiple upsets in a SEU tolerant 8051 micro-controller. In: IEEE Latin
American Test Workshop (3. : 2002 : Montevideu). Digest
of papers. [Amissville : IEEE Computer Society], 2002. p. 120-125 : il. Neuberger, Gustavo. Neuberger,
Gustavo. Lima, Fernanda Gusmao de. Reis, Ricardo Augusto da
Luz. Designing a Reed-Solomon Core Optimized for Area and Performance. In:
South Symposium on Microelectronics (17. : 2002 : Canela). Proceedings. Porto
Alegre : Instituto de Informatica da UFRGS, 2002. p. 69-72 : il. Panato, Alex Fragoso. Neuberger, Gustavo. Lazzari, Cristiano. Lima, Fernanda Gusmao de. Reis, Ricardo Augusto
da Luz. Testing a Rijndael
VHDL Description to Single Event Upsets. In: South Symposium on
Microelectronics (17. : 2002 : Canela).
Proceedings. Porto Alegre : Instituto de Inform_tica da UFRGS,
2002. p. 25-28 : il. 2001 Cota, Erika Fernandes. Lima, Fernanda Gusmao de. Rezgui, Sana. Carro, Luigi. Velazco, Raoul. Lubaszewski, Marcelo Soares.
Reis, Ricardo Augusto da
Luz. Synthesis of an 8051-Like Micro-Controller tolerant to transient faults.
In: Journal of electronic testing : theory and
applications. Hingham Vol. 17, no. 2 (2001), p. 149-161 :
il. Lima, Fernanda Gusmao de. Carmichael, C.. Fabula, J.. Padovani,
R.. Reis, Ricardo Augusto da Luz. A Fault injection analysis of virtex FPGA
TMR design methodology [recurso eletr_nico].
In: European Conference on Radiation and its Effects on Componentes
and Systems (6. : 2001 : Lima, Fernanda Gusmao de. Rezgui, Sana. Carro, Luigi. Velazco, Raoul.
Reis, Ricardo Augusto da Luz. On
the use of VHDL simulation and emulation to derive error rates [recurso eletr_nico]. In:
European Conference on Radiation and its Effects on Componentes
and Systems (6. : 2001 : CARCAMICHAEL, C.; FULLER, E.; FABULA, J.; 2000 Lima, Fernanda Gusmao de. Cota, Erika Fernandes. Carro, Luigi.
Lubaszewski, Marcelo Soares. Reis,
Ricardo Augusto da Luz.
Designing and testing a radiation hardened 8051-like micro-controller. In:
Military and Aerospace Applications of Programmable Devices and Technologies
International Conference (2000 : Lima, Fernanda Gusmao de. Cota, Erika Fernandes. Carro, Luigi.
Lubaszewski, Marcelo Soares. Reis, Ricardo Augusto da Luz. Velazco, Raoul. Rezgui, Lima, Fernanda Gusmao de. D'Avila, Eduardo Rocha. Moraes, Maur_cio
Coutinho. Lubaszewski, Marcelo Soares.
Reis, Ricardo Augusto da
Luz. Using built-in current sensor in field programmable gate arrays. In:
Computa?_o Reconfigur_vel. Mar_lia: FEESR, 2000 p. 142-150 : il. Lima, Fernanda Gusmao de. Cota, Erika Fernandes. Carro, Luigi.
Lubaszewski, Marcelo Soares. Reis, Ricardo Augusto da Luz. Velazco, Raoul.
Rezgui, Sana. SEU hardned 8051-like micro-controller. In: UFRGS
Microeletronics Seminar (15. : 2000 : Torres, RS). Proceedings. Porto Alegre
: Instituto de Inform_tica, 2000. p. 25-28 Lima, Fernanda Gusmao de. Guntzel, Jose Luis Almada. Componentes
program_veis. In: Escola de Microeletronica da Sbc-Sul (2. : 2000 31 jul.- 5
ago. : Torres). Livro texto. Porto Alegre : Instituto de Informatica da UFRGS,
2000. p. 71-96 : il. Lima, Fernanda Gusmao de. D'Avila, Eduardo Rocha. Moraes, Maur_cio
Coutinho. Lubaszewski, Marcelo Soares. Reis, Ricardo Augusto da Luz. A Self-Testing Mask Programmable Matrix using
Built-in Current Sensing. In: IEEE Latin American Test Workshop (1. : 2000 mar. 13-15 : Lima, Fernanda Gusmao de. Barcelos, Marcelo Boeira de. Rochol,
Juergen. Bampi, Sergio. Reis, Ricardo Augusto da Luz. A Frame stream controller IP. In: IEEE
International Symposium on Circuits and Systems (2000 May 28-31 : Lima, Fernanda Gusmao de. Johann, Marcelo de Oliveira. Guntzel,
Jose Luis Almada. D'Avila, Eduardo Rocha. Carro, Luigi. Reis, Ricardo Augusto
da Luz. Designing a mask
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Tatiana Gadelha. Santos, Rafael Ramos dos. Barcelos, Marcelo Boeira de. Buss,
Marcio. Fragoso, Joao Leonardo. Lima, Fernanda Gusmao de. Ferreira, Fabio
Klein. Costa, Eduardo Antonio Cesar da. Reis, Ricardo Augusto da Luz._____
Lawai : uma alternativa para a interligacao lan's a grande distancia. In:
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S.R.L.], 1999. p. 325-333 : il. D'Avila, Eduardo Rocha. Lima, Fernanda Gusmao de. Reis, Ricardo
Augusto da Luz. Edif to blif converter. In: UFRGS Microelectronics Seminar (14. : 1999, july 9-10 : Lima, Fernanda Gusmao de. Projeto com matrizes de c_lulas l_gicas
program_veis. 1999. 126 p. : il. Disserta?_o (mestrado)-Universidade Federal
do Rio Grande do Sul. Instituto de Inform_tica. Programa de P_s-Gradua?_o em
Computa?_o. Porto Alegre, BR-RS, 1999. Ori.: Reis, Ricardo Augusto da Luz. Lima, Fernanda Gusmao de. Johann, Marcelo de Oliveira. Guntzel,
Jose Luis Almada. Carro, Luigi. Reis, Ricardo Augusto da Luz. Programa_de_tv
tool. In: UFRGS Microelectronics Seminar (14. : 1999, july 9-10 : Pelotas,
Brs). Proceedings. Porto Alegre : Instituto de Informatica da UFRGS, 1999. p.
91-94 : il. Lima, Fernanda Gusmao de. Johann, Marcelo de Oliveira. Guntzel,
Jose Luis Almada. D'Avila, Eduardo Rocha. Carro, Luigi. Reis, Ricardo Augusto
da Luz. Maragata. In: UFRGS Microelectronics Seminar (14. : 1999, july 9-10 :
Pelotas, Brs). Proceedings. Porto Alegre : Instituto de Informatica da UFRGS,
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gates functionality. In: Symposium on Integrated Circuits and Systems Design
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gate array. In: UFRGS Microelectronics Seminar (13. : 1998,
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Luz. On the applicability of universal logic gates for designing masked
programmable gate array architectures. In: Workshop Iberchip (4. : 1998, mar. 11-13 : Mar
del Plata, Ar). [anais]. Mar del Plata : Universidad Nacional de la Plata,
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Improving logic density of qcl masterslices
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da Luz. Desenvolvimento de um conversor para viabilizar a sintese de
circuitos integrados a partir de uma descricao vhdl. In: Salao de Iniciacao
Cientifica (10. : 1998 : Porto Alegre). Livro de resumos. Porto Alegre :
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Alegre, Brs). Reis, Ricardo Augusto da Luz. Wagner, Tiaraju Vasconcellos.
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de Mattos. Ori.: Lopes, Artur Oscar. Graduate Thesis: 1999 -
M.Sc. report: Maragata – Mask Programmable Gate Array 2003 -
Qualifying report: Single Event Upset mitigation techniques for
programmable devices -
Thesis Proposal report: Designing SEU mitigation techniques for large
SRAM-based FPGAs [presentation] -
Ph.D. Thesis report: Designing SEU mitigation
techniques for large SRAM-based FPGAs |
