-- Simple Adder with selectable output - Marcelo Johann - UFRGS - 2010
-- 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity somador is

port (	a		: in std_logic_vector ( 3 downto 0);
		b		: in std_logic_vector ( 3 downto 0);
		sel: in std_logic_vector ( 1 downto 0);
		show  : out std_logic_vector(6 downto 0)
	);
end somador;

architecture teste of somador is 
signal soma : std_logic_vector(3 downto 0);

begin
process(a,b,sel)
  begin
    case sel is
    when "10" => soma <= a;
    when "01" => soma <= b;
    when "00" => soma <= a + b;
    when others => soma <= "0000";
    end case;
end process;
    
process(soma)
begin
  case soma is
  when "0000" => show <= "0000001" ;
  when "0001" => show <= "1001111" ;
  when "0010" => show <= "0010010" ;
  when "0011" => show <= "0000110" ;
  when "0100" => show <= "1001100" ;
  when "0101" => show <= "0100100" ;
  when "0110" => show <= "0100000" ;
  when "0111" => show <= "0001111" ;
  when "1000" => show <= "0000000" ;
  when "1001" => show <= "0000100" ;
  when "1010" => show <= "0000010" ;
  when "1011" => show <= "1100000" ;
  when "1100" => show <= "0110001" ;
  when "1101" => show <= "1000010" ;
  when "1110" => show <= "0010000" ;
  when "1111" => show <= "0111000" ;
  when others => show <=  "1111111" ;
  end case;
end process;
end teste;