INTERNATIONAL BOOK CHAPTERS

1. ANCEAU, F. & REIS, Ricardo Augusto da Luz. Design Strategy for VLSI. In: VLSI Architecture. Englewood Cliffs, Prentice-Hall, 1983. Cap. 11, p. 128-37.

2. REIS, Ricardo Augusto da Luz; WAGNER, Flavio Rech. Brazilian Computer Society. In: 36 Years of IFIP. Laxenburg, IFIP, C1996. P. 177-181.

3. REIS, André; REIS, Ricardo.; ROBERT, Michel; AUVERGNE, Daniel. Library Free Technology Mapping. In: VLSI: Integrated Systems on Silicon, Chapman-Hall, 1997, pg. 303-314.

4. MORAES, Fernando; REIS, Ricardo; LIMA, Fernanda. Efficient Layout Style for Three-Metal CMOS Macro-Cells. In: VLSI: Integrated Systems on Silicon, Chapman-Hall, 1997, pg. 415-426.

5. LIMA, Fernanda G..; JOHANN, Marcelo.; GÜNTZEL, José; D’AVILA, Eduardo; CARRO, Luigi; REIS, Ricardo A. L. Designing a Mask Programmable Matrix for Sequencial Circuits. In: VLSI: Systems on Chip, Kluwer Publishers, Boston, 2000. p. 439-446.

6. REIS, Ricardo; Introdução IN: Sistemas Digitales: Síntese Física de Circuitos Integrados, Edições CYTED- Uniandes, Bogotá, 2000. pg.1-10, ISBN: 958-695-038-7

7. REIS, Ricardo; Implementação de Portas Lógicas IN: Sistemas Digitales: Síntese Física de Circuitos Integrados, Edições CYTED- Uniandes, Bogotá, 2000. pg.55-73, ISBN: 958-695-038-7

8. REIS, Ricardo; REIS, André; Ferramentas de CAD IN: Sistemas Digitales: Síntese Física de Circuitos Integrados, Edições CYTED- Uniandes, Bogotá, 2000. pg.131-152, ISBN: 958-695-038-7

9. INDRUSIAK, L., BECKER, J., GLESNER, M., REIS, R. A. L., Distributed Collaborative Design Over Cave Framework In: SOC Design Methodologies. Ed. Londres, Kluwer, 2002

10. CASSEL, L. et al (inc. REIS. R). Computing: The Shape of an Evolving Discipline. IN: Informatics Curricula, KLUWER Publishers, Boston, 2003

11. REIS, R., MORAES, F., Geração Automática de Leiaute. IN: Sistemas Digitales: Metodologias de Diseno VLSI, Edições CYTED- Uniandes, Bogotá, 2003, pg. 67-100, ISBN 958-695-075-1

12. REIS, R., Geração de Circuitos com Standard Cells. IN: Sistemas Digitales: Metodologias de Diseno VLSI, Edições CYTED- Uniandes, Bogotá, 2003. pg. 51-66, ISBN 958-695-075-1

13. BARCELOS, M.; PANATO, A.; REIS, R., Estudo de Caso: Circuito de Criptografia. IN: Sistemas Digitales: Metodologias de Diseno VLSI, Edições CYTED- Uniandes, Bogotá, 2003. pg. 169-208, ISBN 958-695-075-1

14. HENTSCHKE, R.; REIS, R., Estudo de Caso: Projeto de um ASIC para Criptografia. IN: Sistemas Digitales: Metodologias de Diseno VLSI, Edições CYTED- Uniandes, Bogotá, 2003, pg. 209-222, ISBN 958-695-075-1

15. REIS, R., JESS, J. Design of System on a Chip: Introduction, IN: Design of System on a Chip, Devices & Components, KLUWER ACADEMIC PUBLISHERS, Boston, 2004, p. 7- 18. ISBN 1-4020-7928-1.

16. REIS, R., Requirements for Computer-Aided Learning from the Point of View of Electronic Design. IN: EDUTECH: Computer-Aided Design Meets Computer-Aided Learning. KLUWER ACADEMIC PUBLISHERS, Boston, 2004, p. 63-68. ISBN 1-4020-8161-8.

17. LUBASZEWSKI, L.; REIS, R., JESS, J. Design of System on a Chip: Introduction, IN: Design of Systems on a Chip: Design & Test, Springer, June 2006. ISBN 0-387-32499-2. Pp. 1- 7.

18. REIS, R.; GUNTZEL, J. JOHANN, Marcelo. Physical Design Automation, IN: Design of Systems on a Chip: Design & Test, Springer, June 2006. ISBN 0-387-32499-2. pp. 83- 108

19. LAZZARI, C., DOMINGUES, C., GUNTZEL, J.; REIS, R., A Novel Full Automatic Layout Generation Strategy for Static CMOS. IN: VLSI-SOC: From Systems to Chips. Springer. May 2006. ISBN 0-387-33402-5.

20. OLIVEIRA, L.; COSTA, E.; MONTEIRO, J.; MARTINS, J.; BAMPI, S.; SANTOS, C.; FERRÃO, D.; REIS, R.; A Comparison of Layout Implementations of Pipelined And Non-Pipelined Signed Radix-4 Array Multiplier And Modified Booth Multiplier Architectures. IN: VLSI-SOC: From Systems to Silicon. Springer, 2007, ISBN 978-0-387-73660-0. pp. 25-39

21. MARCON, C.; PALMA, J.; CALAZANS, MORAES, F.; SUSIN, A.; REIS, R.; Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. IN: VLSI-SOC: From Systems to Silicon. Springer, 2007, ISBN 978-0-387-73660-0. Pp. 179-194.

22. LAZZARI, C., ANGHEL, L.; REIS, R., A Transistor Placement Technique Using Genetic Algorithm And Analytical Programming. IN: VLSI-SOC: From Systems to Silicon. Springer, 2007, ISBN 978-0-387-73660-0. pp. 331- 344.

23. KASTENSMIDT, Fernanda; REIS, Ricardo, Fault Tolerance in Programmable Circuits. IN: Radiation Effects on Embedded Systems, Springer, 2007, ISBN 978-1-4020-5645-1. pp. 161- 181. 10.1007/978-1-4020-5646-8_8

24. HENTSCHKE, R.; SAWICKI, S., JOHANN, M., REIS, R., An Algorithm for I/O Pins Partitioning and Placement Targeting 3D VLSI Circuits IN: VLSI-SoC: Research Trends in VLSI and Systems on Chip, Springer, January 2008, ISBN 978-0-387-74908-2. pp. 255-275.

25. NEUBERGER, G., KASTENSMIDT, F., REIS, R., WIRTH, G., BREDERLOW, R., PACHA, C., Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies, IN: VLSI-SoC: Advanced Topics on Systems on Chip, Springer, 2009, p. 1-16, ISBN 978-0-387-89557-4. DOI 10.1007/978-0-387-89558-1_1

26. BRUSAMARELLO, L., SILVA, R., WIRTH, G., REIS, R., Statistical and Numerical Approach for a Computer Efficient Circuit Yield Analysis, IN: VLSI-SoC: Advanced Topics on Systems on Chip, Springer Science, 2009, p. 161-184, ISBN 978-0-387-89557-4. DOI: 10.1007/978-0-387-89558-1_9

27. REIS, R., Design Tools and Methods for Chip Physical Design, IN: Multiprocessor System-on-Chip: Hardware Design and Tool Integration, Editors: Hübner, Michael; Becker, Jürgen, Springer Science, 2011, p. 155-166, ISBN 978-1-4419-6459-5, DOI 10.1007/978-1-4419-6459-5

28. BAMPI, S., REIS, R., Challenges and Emerging Technologies for System Integration Beyond the End of the Roadmap of Nano-CMOS, IN: VLSI-SoC: Technologies for Systems Integration, Editors: Becker, Jürgen; Johann, Marcelo; Reis, Ricardo. Springer, p. 21-33, 2011, IFIP AICT 360, ISBN 978-3-642-23119-3.

29. KASTENSMIDT, F., REIS, R., Soft Error Rate and Fault Tolerance Techniques for FPGAs, In: REIS, R., CAO, Y., WIRTH, G., Circuit Design for Reliability, Springer, 2015, p. 207-221, ISBN 978-1-4614-4077-2, DOI 10.1007/978-1-4614-4078-9__10

30. REIS, R., CAO, Y., WIRTH, G., Introduction, In: REIS, R., CAO, Y., WIRTH, G., Circuit Design for Reliability, Springer, 2015, p. 1-4, ISBN 978-1-4614-4077-2, DOI 10.1007/978-1-4614-4078-9__1

31. TONFAT, J., TARRILLO, J., TAMBARA, L., KASTENSMIDT, F., REIS, R., Multiple Fault Injection Platform for SRAM-Based FPGA Based on Ground-Level Radiation Experiments, In: KASTENSMIDT, F., RECH., P., FPGAs and Parallel Architectures for Aerospace Applications, Springer, 2016, p. 135-151, ISBN: 978-3-319-14351-4, DOI: 10.1007/978-3-319-14352-1_10