INTERNATIONALS JOURNALS

1. ANCEAU, François e REIS, Ricardo Augusto da Luz, Complex Integrated Circuit Design Strategy, IEEE Journal of Solid State Circuits, New York, SC-17(3):459-64, June 1982.

2. REIS, Ricardo Augusto da Luz, Topological Evaluation of VLSI Circuits, Revista de Informática & Automática, Madrid 17(59) 26-33, 1984

3. REIS, André; ROBERT, Michel; AUVERGNE, Daniel; REIS, Ricardo. Associating CMOS Transistors with BDD Arcs for Technology Mapping. IEE Electronics Letters, 6th July 1995, Vol. 31, No. 14, pp. 1118-20.

4. INDRUSIAK, Leandro; REIS, Ricardo. 3D Integrated Circuit Layout Visualization using VRML, In: Future Generation Computer Systems, Elsevier Science, Vol 17, Issue 5, March 2001, pg. 503–511.

5. Cota E., Lima F., Rezgui S., Carro L., Velazco R., Lubaszewski M., Reis R., Synthesis of an 8051-like Micro-Controller Tolerant to Transient Faults, JETTA - JOURNAL OF ELECTRONIC TESTING, THEORY AND APPLICATIONS, Kluwer Academic Publishers, Volume 17, Issue 2, April 2001 ISBN: 0923-8174, DOI 10.1023/A:1011125927317.

6. NEUBERGER, G.; LIMA F., CARRO L., REIS R., A Multiple Bit Upset Tolerant SRAM Memory, ACM TODAES – Transaction on Design Automation of Electronic Systems, v. 8, Num. 4, October 2003, p. 577-590. ISSN 1084-4309. DOI 10.1145/944027.944038

7. LIMA F., NEUBERGER, G.; HENTSCHKE, R.; CARRO L., REIS R., Designing Fault-Tolerant Techniques for SRAM-based FPGAs, IEEE Design&Test, November/December 2004. p. 552-562. ISSN 0740-7475. DOI 10.1109/MDT.2004.85

8. NEUBERGER, G., LIMA F., REIS R., Designing an Automatic Technique for Optimization of Reed-Solomon Codes to Improve Fault-tolerance in Memories. IEEE Design&Test, January/February 2005, P. 50-58. ISSN 0740-7475. DOI 10.1109/MDT.2005.2

9. INDRUSIAK, L.S., GLESNER, M., REIS, R.. Introducing Remote Prototyping Labs into the Design Flow for Application-Specific Digital Electronic Systems: the Evolution of a Concept. IEEE Transactions on Industrial Electronics, December 2007, Vol. 54, Issue 6, pp. 3069-3077, ISSN: 0278-0046, DOI 10.1109/TIE.2007.907010.

10. HAN, S.; CHAE, S.; BRISOLARA L. ; CARRO, L. ; REIS, R.; GUERIN, X.; JERRAYA, A., Memory-Efficient Multithread Code Generation From Simulink for Heterogeneous MPSoC. IN: Design Automation of Embedded Systems. Springer, ISSN: 0929-5585 (print version), ISSN: 1572-8080 (electronic version), Issue Volume 11, Number 4 / December, 2007, Pages 249-283. DOI 10.1007/s10617-007-9009-4.

11. LAZZARI, C., REIS, R., ANGHEL, L. A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis, JETTA: Journal of Electronic Testing: Theory and Applications, Springer, ISSN 0923-8174 (Print) 1573-0727 (Online), Volume 23, Number 6, pp. 625-633, December 2007. DOI: 10.1007/s10836-007-5055-x.

12. BRUSAMARELLO, L., DA SILVA, R., WIRTH, G., REIS, R., Probabilistic Approach for Yield Analysis of Dynamic Logic Circuits, IEEE Transactions on Circuits and Systems I, Vol.55, Issue8, September 2008, PP. 2238-2248, ISSN 1549-8328. DOI: 10.1109/TCSI.2008.918141.

13. BASTOS, R., KASTENSMIDT, F., REIS, R. Design of a Soft-Error Robust Microprocessor, Microelectronics Journal, V. 40, N. 7, Elsevier Publishers, ISSN: 0026-2692, July 2009, p. 1062-1068. DOI: 10.1016/j.mejo.2008.10.001

14. HENTSCHKE, R., NARASIMHAM, J., JOHANN, M., REIS, R., Maze Routing Steiner Trees With Delay vs. Wire Length Trade-off, IEEE Transactions on Very Large Scale Integration, Volume 17, Issue 8, ISSN 1063-8210, August 2009, p. 1073-1086. DOI: 10.1109/TVLSI.2009.2019798

15. BASTOS, R., SICARD, G., KASTENSMIDT, F., RENAUDIN M., REIS, R., Asynchronous Circuits as Alternative for Mitigation of Long-Duration Transient Faults in Deep-Submicron Technologies, Microelectronics Reliability, Volume 50, Issues 9–11, September–November 2010, p. 1241-1246, published by Elsevier B.V. in 2010. ISSN: 0026-2714. DOI: 10.1016/j.microrel.2010.07.014

16. BRUSAMARELLO, L., NEUBERGER, G., WIRTH, G., DA SILVA, R., REIS, R., MURGAI, R., REDDY, S., WALKER, W. Statistical Analysis of Hold Time Violations, Journal of Computational Electronics, published by Springer, Vol. 9, Number 3-4, 2010, p. 114-121, ISSN: 1569-8025, DOI: 10.1007/s10825-010-0322-y

17. SAWICKI, S., WILKE, G., JOHANN, M., REIS, R., 3D-Via Driven Partitioning for 3D VLSI Integrated Circuits, CLEI Electronic Journal, VOLUME 13, NUMBER 3, PAPER 1, DECEMBER 2010, Special issue of best papers presented at CLEI'2009 (revised version), 11 pages, ISSN 0717- 5000.

18. LAZZARI, C., WIRTH, G., KASTENSMIDT, F., ANGHEL, L., REIS, R., Asymmetric Transistor Sizing Targeting Radiation-Hardened Circuits, Journal on Electrical Engineering, Springer, DOI10.1007/s00202-011-0212-8, June 2011.

19. VIOLANTE, M., MEINHARDT, C., REIS, R., REORDA, M., A Low-Cost Solution for Deploying Processor Cores in Harsh Environments, IEEE Transactions on Industrial Electronics, Vol. 58, Issue 7, p. 2617- 2626, July 2011, ISSN: 0278-0046, DOI: 10.1109/TIE.2011.2134054

20. VAZQUEZ, J., CHAMPAC, V., ZIESEMER, A., REIS, R., TEIXEIRA, I., SANTOS, M. and TEIXEIRA, P., Delay Sensing for Long-Term Variations and Defects Monitoring in Safety–Critical Applications, IN: Analog Integrated Circuits and Signal Processing, Volume 70, Number 2, 249-263, February 2012, Springer, ISSN 0925-1030, DOI: 10.1007/s10470-011-9789-0.

21. GUTHAUS, M., HU, X., WILKE, G., FLACH, G., REIS, R., High-Performance Clock Mesh Optimization, ACM TODAES - ACM Transactions on Design Automation of Electronic Systems, Vol. 17, Issue 3, DOI: 10.1145/2209291.2209306, ISSN:1084-4309, EISSN:1557-7309, June 2012.

22. POSSER, G., FLACH, G., WILKE, G., REIS, R., Gate Sizing using Geometric Programming, IN: Analog Integrated Circuits and Signal Processing, Volume 73, Number 3, 831-840, December 2012, Springer, ISSN 0925-1030, DOI: 10.1007/s10470-012-9943-3.

23. GUTHAUS, M., WILKE, G., REIS, R., Revisiting Automated Physical Synthesis of High-Performance Clock Networks, ACM TODAES - ACM Transactions on Design Automation of Electronic Systems, Vol. 18, Issue 2, DOI: 10.1145/2442087.2442102, ISSN: 1084-4309, EISSN:1557-7309, March 2013.

24. FLACH, G., REIMANN, T., POSSER, G., JOHANN, G., REIS, R., An Effective Method for Simultaneous Gate Sizing and Vth Assignment using Lagrangian Relaxation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 33, Issue 4, April 2014, p. 546-557, DOI: 10.1109/TCAD.2014.2305847, ISSN 0278-0070

25. MEINHARDT, C., ZIMPECK, A., REIS, R., Predictive Evaluation of Electrical Characteristics of Sub-22nm Finfet Technologies Under Device Geometry Variations, Microelectronics Reliability, Volume 54, Issues 9–10, September–October 2014, Pages 2319-2324, published by Elsevier B.V. in 2014. ISSN: 0026-2714, DOI: 10.1016/j.microrel.2014.07.023

26. KASTENSMIDT, F., TONFAT, J., BOTH, T., RECH, P., WIRTH, G., REIS, R., BRUGUIER, F., BENOIT, P., TORRES, L., FROST, C., Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs, Microelectronics Reliability, Volume 54, Issues 9–10, September–October 2014, Pages 2344-2348, published by Elsevier B.V. in 2014. ISSN: 0026-2714, DOI: 10.1016/j.microrel.2014.07.

27. ZIMPECK, A., MEINHARDT, C., REIS, R., Impact of PVT Variability on 20nm FinFET Standard Cells, Microelectronics Reliability, Volume 55, Issues 9–10, August–September 2015, Pages 1379–1383, published by Elsevier B.V., 2015. ISSN: 0026-2714. doi:10.1016/j.microrel.2015.06.039

28. ROSA, F., BRUM, R., OST, L., WIRTH, G., KASTENSMIDT, F., REIS, R., Impact of Dynamic Voltage Scaling and Thermal Factors on SRAM Reliability, Microelectronics Reliability, Volume 55, Issues 9–10, August–September 2015, Pages 1486–1490, published by Elsevier B.V., 2015. ISSN: 0026-2714, doi:10.1016/j.microrel.2015.07.013.

29. TONFAT, J., KASTENSMIDT, F., RECH, P., REIS, R., QUINN, H., Analyzing the Effectiveness of a Frame-level Redundancy Scrubbing Technique for SRAM-based FPGAs, IEEE Transactions on Nuclear Science, Vol. 62, No. 6, December 2015, p. 3080-3087, ISSN: 0018-9499, DOI: 10.1109/TNS.2015.2489601.

30. ZIESEMER, A., REIS, R., Physical Design Automation of Transistors Network, Microelectronics Engineering, V. 148, p. 122-128, December 2015, Elsevier B.V., doi:10.1016/j.mee.2015.10.018

31. REIMANN, T., SZE, C., REIS, R., Challenges of Cell Selection Algorithms in Industrial High Performance Microprocessor Designs, Integration, Elsevier B. V., Volume 52, January 2016, Pages 347-354, ISSN: 0167-9260, doi:10.1016/j.vlsi.2015.09.001

32. POSSER, G., MISHRA, V., JAIN, P., REIS, R., SAPATNEKART, S., Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 35, N.2, February 2016, p. 220-231, ISSN 0278-0070, DOI: 10.1109/TCAD.2015.2456427.