Programação >> Prof. Ricardo Reis Palestrante Prof. Ricardo Reis, Universidade Federal do Rio Grande do Sul - Porto Alegre, Brazil Título EDA at Transistor Level Slide da Apresentação (.pdf) New Abstract The research and development of the design automation of integrated circuits started by the layout level and it evolved to higher levels of abstraction. At physical design level the evolution of automation was remained at the standard cell approach, where the layout of the cells are designed and included in a cell library. So, the design of the cell layout is not really automated. A cell library is also limited to small number of logic combinations. This limitation doesn't allow reaching an optimization of the circuit at the physical design level. The talk details a new approach where all logic cells are designed on the fly, without the limitations that we have when using a cell library (number of functions, number of transistors, transistor sizing, area and power consumption). The cell generator allows the automatic design of cells having any transistor network (using simple gates or static CMOS complex gates-SCCG) and any transistor sizing. When the size of the transistor should be bigger than the cell height, the tool is able to do transistor folding. As the designer is free of the limitations of a cell library, it is possible to do a deep logic minimization where all needed logic cells will be generated on the fly. This allows a reduction on the number of needed transistors to implement a circuit. As consequence, the static power consumption will also be reduced. The cell generator provides cells with a compacted layout, allowing a significant transistor density. The talk will give more details about physical design automation strategies related to transistor topologies, management of routing in all layers, VCC and Ground distribution, clock distribution, contacts and vias management, body ties management, transistor sizing and folding and the how these strategies can improve the layout optimization. Some results will be compared with the ones obtained with traditional standard cells tools (vendor's tools), showing a gain in area, delay and consumption. The flexibility of the approach can also let the designers to define the layout parameters to cope with problems like tolerance to transient effects, yield improvement, printability, etc. The designer can also manage the sizing of transistors to reduce power consumption, without compromising the clock frequency.