Programação >> Prof. Arturo Sarmiento Reyes (INAOE, Mexico) Speaker Prof. Arturo Sarmiento Reyes (INAOE, Mexico) Title CMOS + SET Towards Hybrid Simulation Abstract Recent remarkable developments are taking place in electronics: on one side the continuously downscaling of CMOS devices and the advent of nanodevices such as the single-electron transistors (SETs) and memristors. In first place, nanometric CMOS transistors exhibit phenomena that were not taken into account for previous larger dimensions and this technology is pushed into its limits. In second place, SE Devices are foreseen as basic cells for future electronic design. The main obstacle when tackling the problem of simulating hybrid SET/MOS circuits resides in the fact that the mechanism of current flow differs from one device to another, namely MOS devices have a continuum in the way the current is transported, while in SEDs a discrete mechanism has place. Besides, modern IC design methodologies resort to well-established EDA tools, such as SPICE-like simulators in order to verify the design. Therefore, when establishing a simulation methodology for hybrid circuitry, it becomes mandatory to adequate the models for the SEDs to circuit-level in order to make them usable within current simulation tools. SHORT CVs Arturo Sarmiento Reyes obtained his Bachelor's degree in electronic engineering from the Technological Institute at Veracruz, Mexico, his MSc degree in electronics from the National Institute for Astrophysics, Optics and Electronics (INAOE) at Mexico, and his PhD from the Delft University of Technology at The Netherlands. Currently he works as a researcher at INAOE where he is the Head of the Electronics Department since 2006. He has authored nearly 75 papers in journals and scientific conferences. He is the Chair of the CAS Chapter of the IEEE Puebla Section. His fields of interest are: circuit simulation, design methodologies, nonlinear network theory, and development of CAD tools.