Poster Session 1: Thursday, October 22.

 

1.1.         

Logic Synthesis to Automatic Cell Layout Generation

Calebe Conceição and Ricardo Reis, UFRGS

1.2.         

Logic Minimization by Gate Merging

Luciana Mendes Da Silva, Calebe Micael de Oliveira Conceição, Guilherme Bontorin and Ricardo Reis, UFRGS

1.3.         

Local search techniques for incremental timing-driven placement

Mateus Fogaça, Guilherme Flach, Marcelo Johann, Ricardo Reis and Jucemar Monteiro, UFRGS

1.4.         

Test Solutions for NAND Flash Products - eMMC Test Solution

Elcio Kondo, Magrit Krug, Marcio Da Silva, Lucio Prade, Celso Peter and Fabiano Colling, Unisinos

1.5.         

3D Sound Perception using Stereo Headphones

Joel A. Luft and Altamiro A. Susin, UFRGS

1.6.         

Asynchronous VLSI Design: Circuit Templates, Cell Libraries and Synthesis Flows

Matheus Moreira and Ney Calazans, PUCRS

1.7.         

Automatic Synthesis of Layout with ASTRAN

Gisell Moura, Adriel Ziesemer and Ricardo Reis, UFRGS

1.8.         

A Multi-Standard Interpolation Hardware Solution for H.264 and HEVC

Guilherme Paim, Henrique Maich, Vladimir Afonso, Luciano Agostini, Bruno Zatt and Marcelo Porto, UFPel

1.9.         

Stereo Matching and Sensor Fusion Technique for Image Depth Estimation

Fabio Pereira and Altamiro Susin, UFRGS

1.10.      

Jezz: An Efficient Legalization Algorithm

Julia Puget, Guilherme Flach, Marcelo Johann and Ricardo Reis, UFRGS

1.11.      

PHiCIT - Improving Hierarchical Networks-on-chip through 3D Silicon Photonics Integration

Cezar Rodolfo Wedig Reinbrecht, Martha J. Sepúlveda and Altamiro Amadeu Susin, UFRGS

1.12.      

An Evaluation of BTI Degradation of 32nm Standard Cells

Rafael Schivittz, Cristina Meinhardt and Paulo F. Butzen, FURG

1.13.      

Energy-Efficient Architectures for Sum of Squared Differences Calculation

Ismael Seidel, Marcio Monteiro and Jose Luis Guntzel, UFSC

1.14.      

SATD Hardware Architecture for HEVC Encoder

Bianca Silveira, Claudio Diniz, Eduardo Da Costa and Mateus Fonseca, UCPel

1.15.      

Design Method for CML Topology-Based Divide-by-2 Circuit with Unbalanced Loads

Raphael Souza and Agord Matos, Programa CI-Brasil

1.16.      

Run-time of the Data Dependency Detector for Harvesting Parallelism for Global Routing

Diego Tumelero, Guilherme Bontorin and Ricardo Reis, UFRGS