Poster Session 1: Thursday, October 22.
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1.1.
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Logic Synthesis to Automatic
Cell Layout Generation Calebe Conceição and
Ricardo Reis, UFRGS |
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1.2.
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Logic Minimization by Gate
Merging Luciana
Mendes Da Silva, Calebe Micael de Oliveira
Conceição, Guilherme
Bontorin and Ricardo Reis,
UFRGS |
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1.3.
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Local search techniques for
incremental timing-driven placement Mateus
Fogaça, Guilherme Flach, Marcelo Johann, Ricardo
Reis and Jucemar Monteiro, UFRGS |
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1.4.
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Test Solutions for NAND Flash
Products - eMMC Test Solution Elcio Kondo,
Magrit Krug, Marcio Da
Silva, Lucio Prade, Celso Peter and Fabiano Colling, Unisinos |
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1.5.
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3D Sound Perception using
Stereo Headphones Joel
A. Luft and Altamiro A. Susin,
UFRGS |
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1.6.
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Asynchronous VLSI Design:
Circuit Templates, Cell Libraries and Synthesis Flows Matheus
Moreira and Ney Calazans, PUCRS |
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1.7.
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Automatic Synthesis of Layout
with ASTRAN Gisell Moura, Adriel Ziesemer and Ricardo Reis, UFRGS |
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1.8.
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A Multi-Standard Interpolation
Hardware Solution for H.264 and HEVC Guilherme
Paim, Henrique Maich, Vladimir Afonso, Luciano
Agostini, Bruno Zatt and
Marcelo Porto, UFPel |
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1.9.
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Stereo Matching and Sensor
Fusion Technique for Image Depth Estimation Fabio Pereira and
Altamiro Susin, UFRGS |
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1.10.
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Jezz: An Efficient Legalization Algorithm Julia
Puget, Guilherme Flach, Marcelo
Johann and Ricardo Reis, UFRGS |
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1.11.
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PHiCIT - Improving Hierarchical Networks-on-chip
through 3D Silicon Photonics Integration Cezar
Rodolfo Wedig Reinbrecht,
Martha J. Sepúlveda and Altamiro Amadeu Susin, UFRGS |
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1.12.
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An Evaluation of BTI
Degradation of 32nm Standard Cells Rafael Schivittz,
Cristina Meinhardt and
Paulo F. Butzen, FURG |
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1.13.
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Energy-Efficient Architectures
for Sum of Squared Differences Calculation Ismael
Seidel, Marcio Monteiro and Jose
Luis Guntzel, UFSC |
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1.14.
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SATD Hardware Architecture for
HEVC Encoder Bianca Silveira, Claudio Diniz, Eduardo Da Costa and Mateus Fonseca, UCPel |
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1.15.
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Design Method for CML Topology-Based Divide-by-2 Circuit with Unbalanced Loads Raphael
Souza and Agord Matos, Programa CI-Brasil |
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1.16.
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Run-time of the Data Dependency
Detector for Harvesting Parallelism for Global Routing Diego
Tumelero, Guilherme Bontorin
and Ricardo Reis, UFRGS |