Co-located with EMicro2016 and ASYNC2016

Porto Alegre, Brazil

May 11 to 14, 2016


Registration to EMICRO/SIM 2016 is now opened! Regular and discount prices for SBC, SBMicro and IEEE members are shown in the table below. Early-bird registration rates are valid until May 5.

International attendees are advised to register using their credit cards.

Click LINK to proceed with your registration.

The topics include, but are not limited to:

  • Analog/mixed-signal circuits
  • Imaging and image sensors
  • CAD and design tools
  • Low-power low-voltage designs
  • Microsystems Computer architecture and memories
  • Digital circuits
  • Sensory circuits and systems
  • Digital signal processing
  • Technology Trends
  • Embedded systems
  • Test and verification


  • Full paper submission Deadline: March 23th, 2016 [EXTENDED]
    Notification of acceptance: March 28, 2016
    Final manuscript: April 4, 2016
  • Information for authors:
    The article should be written in English with a maximum of 4 pages and using the template available below.
    Papers should be submited in PDF format.
    The first page should contain the title of the article, the authors name, e-mail and abstract .
    The article text begins immediately after the abstract.
    Whenever possible, avoid the use of footnotes.
    Paper submission should be done by EasyChair site . To submit your article, you must sign up for free at EasyChair which can be accessed through the submission button below.

  • Authors of selected number of undergraduate high quality papers will be invited to submit an extended version of their work to the ICCEEG journal, Special Issue.


Wednesday, May 11


  • Local: PUCRS - FACIN (Prédio 32) - Hall
  • Subject: Check the ASYNC'2016 program for more information
  • Local: PUCRS - FACIN (Building 32) - Amphitheater
  • Check ASYNC'2016 program: Link
  • Subject: Check the ASYNC'2016 program for more information
  • Local: PUCRS - FACIN (Building 32) - Amphitheater
  • Check ASYNC'2016 program: Link
  • Speaker: Ken Stevens
  • Institution: University of Utah, USA
  • Subject: The Periodic Laws of Circuit Design
  • Local: PUCRS - FACIN (Building 32) - Amphitheater
  • Abstract: As elegantly stated by Gaius Cornelius Tacitus: "In all things there is a law of cycles".  It is clear that we are daily surrounded by cycles in nature, from the spin and orbit of the earth, to the periodic structure of the natural elements from which it is built. In this presentation I will argue that the digital circuits that we build are no different: the elements of circuit design are periodic, just as are the natural physical elements.  This presentation will weave the periodic nature of circuits into the history of design evolution, and predict whether there will be periodicity in design formalism.  It will include a simple nuts and bolts definition of the art of design, and how digital systems are naturally created "without clocks".  The foundation of design will be argued to itself be based on laws of concurrency and synchronization, and how if properly formed and applied, these laws provide great room for creativity, flexibility, and design freedom as we attempt to build efficient cyclical circuits.
  • Short Bio: Kenneth S. Stevens is an Associate Professor at the University of Utah. Prior to Utah, Ken worked at Intel's Strategic CAD Lab where he developed timing technology for the double frequency ALU cores, multiple input switching validation, and the design of the front end of the Pentium Processor with asynchronous circuits.  Prior to Intel, Ken was an Assistant Professor at the Air Force Institute of Technology (AFIT) in Dayton Ohio where he developed asynchronous communication chips for space applications. Ken received his Ph.D. at the University of Calgary, where he researched the verification of sequential circuits and systems. Before that he worked at Fairchild Labs for AI Research and Hewlett Packard Labs. There he invented an asynchronous circuit synthesis methodology called "burst mode", and designed and fabricated an ultra high bandwidth communication chip for distributed memory multiprocessors. He also received three degrees from the University of Utah, including a B.A. in Biology, and B.S. and M.S. degrees in Computer Science. Ken has published in journals and conferences, has 14 patents, and is a Senior Member of the IEEE.  He also created a successful software startup company, has developed software for the GNU project, and serves on program committees and conference chairmanships. His current research focus includes VLSI design, asynchronous circuits and systems, timing verification, CAD, formal methods, network fabrics, high speed on-chip communication.
  • Speaker: Jordi Cortadella
  • Institution: UPC, Catalunya
  • Subject: Synthesis of asynchronous controllers from Signal Transition Graphs
  • Local: PUCRS - FACIN (Building 32) - Amphitheater
  • Abstract: The lecture will present the core theory for the synthesis of asynchronous controllers from Signal Transition Graphs (STGs). STGs are interpreted Petri nets that represent the relations between signal events in an asynchronous controller, in a similar way as it is specified in a waveform. Asynchronous circuits can be automatically synthesized from an STG using logic synthesis techniques. The lecture will give an overview of the synthesis flow including the specification of controllers, state encoding and synthesis of speed-independent circuits. The lecture will also include a practical demonstration using petrify, a tool that has been widely used during 20 years for the synthesis of controllers and Petri nets.
  • Short Bio: Jordi Cortadella is Professor and Head of the Computer Science Department at the Universitat Politècnica de Catalunya. He is a Fellow of the IEEE and member of the Academia Europaea. He holds a M.S. and a Ph.D. degree in Computer Science (Universitat Politècnica de Catalunya, 1985 and 1987). In 1988, he was a Visiting Scholar at the University of California, Berkeley. His research interests include formal methods and computer-aided design of VLSI systems with special emphasis on asynchronous circuits, concurrent systems and logic synthesis. He has co-authored numerous research papers and has been invited to present tutorials at various conferences. Prof. Cortadella has served on the technical committees of several international conferences in the field of Design Automation and Concurrent Systems and is associate editor of the IEEE Transactions on CAD of Integrated Circuits and Systems. He received best paper awards at the Int. Symp. on Advanced Research in Asynchronous Circuits and Systems (2004), the Design Automation Conference (2004) and the Int. Conf. on Application of Concurrency to System Design (2009). In 2003, he was the recipient of a Distinction for the Promotion of the University Research by the Generalitat de Catalunya.
  • Speaker: TBD
  • Institution: CEITEC
  • Subject: TBD
  • Local: PUCRS - FACIN (Building 32) - Amphitheater
  • Abstract: TBD
  • Short Bio: TBD
  • Speaker: Organization
  • Subject: Opening Session
  • Local: PUCRS - FACIN (Building 32) - Amphitheater

Thursday, May 12


  • Local: UFRGS - INF - Convention Center (Building 43413) - Main Lobby
  • Speaker: Ricardo Reis
  • Institution: UFRGS, Brazil
  • Subject: Introdução ao Projeto de Circuitos Integrados
  • Local: UFRGS - INF - Convention Center (Building 43413) - Lower Auditorium
  • Abstract: A palestra apresentará conceitos básicos de como projetar um circuito integrado e quais são os aspectos importantes na síntese de circuitos integrados de forma a atender o requisitos de consumo, velocidade e área. Será apresentado como implementar equações lógicas a partir de uma rede de transistores (rede de chaves). Os chips usando tecnologias de ultima geração demandam um esforço expressivo em termos de otimização. Para tanto, a qualidade de um projeto depende cada vez mais da qualidade das ferramentas de EDA que são utilizados no projeto. Procurando facilitar a compreensão de quem não atua (ainda) na área de microeletrônica, a palestra fará apoio de muitas ilustrações.
  • Short Bio: Full Professor at Instituto de Informática of the UFRGS (professor since 1979). Electrical Engineering from the UFRGS, Porto Alegre, Brazil, in 1978. Ph.D. degree from the Polytechnic Institute of Grenoble (INPG), France, January 1983. Member of IEEE CASS Distinguished Lecturer Program 2014/2015. Former member of the Microelectronics Committee and Computer Science Committee (two terms) of the National Council for Scientific and Technological Development (CNPq). His primary research interests include Physical Design Automation and Methodologies, CAD tools, Circuits Tolerant to Radiation, VLSI Design Methodologies and Microelectronics Education. More than 500 hundred papers in journals and conferences proceedings. He is also author or co-author of several books. Award as research of the year by the Science Foundation of Rio Grande do Sul, 2002. Silver Core award from IFIP. Meritorious Service Award 2015 by IEEE Circuits and Systems Society. Research level 1A of the CNPq (Brazilian National Science Foundation). Head of several research projects. Past head of the Graduate Program on Microelectronics Graduate Program (two terms) and Computer Science (two terms) at UFRGS. Professor and Advisor at the Microelectronics and Computer Science Graduate Programs at UFRGS. General Chair or Program Chair of several conferences like the IFIP/IEEE VLSI-SoC, IEEE ISVLSI, IEEE LASCAS, Symposium on Integrated Circuits and Systems Design (SBCCI) and Congress of the Brazilian Microelectronics Society (SBMIcro). Past President of the Brazilian Computer Society and Past Vice-President of the Brazilian Microelectronics Society. IEEE CASS Chapter Rio Grande do Sul Chair (since 2007). Vice-president of IEEE Circuits and Systems representing R9, for two terms, from 2008 to 2011. Chair of IFIP TC10. Member of the Editorial Board of IEEE Design&Test and IEEE JETCAS. Member of the Steering Committee of the following conferences: IFIP/IEEE VLSI-SoC, ICECS, LASCAS, NEWCAS, IEEE CASS Summer School, IEEE ISVLSI, SBCCI, PATMOS, IBERCHIP. Ricardo Reis is a senior member of IEEE.
  • Speaker: Patrick Groeneveld
  • Institution: Synopsys, USA
  • Subject: Correct by Construction or Construct by Correction? IC design flows in practice
  • Local: UFRGS - INF - Convention Center (Building 43413) - Lower Auditorium
  • Abstract: This presentation dissects the architecture of modern EDA design flows that are used for billion transistor chips. At its core it is an interaction between complex synthesis and analysis steps. the right sequence of steps gives the best results for large designs, but it turns out to be hard to find a generic recipe that works for arbitrary designs.
  • Short Bio: Patrick Groeneveld had worked on EDA related problems for over a quarter century. He received his masters and Ph.D. degrees in Electrical Engineering from Delft University in 1987 and 1991, respectively. Until 1996 he was research fellow and associate professor at Delft University. At Delft he worked (among others) on one of the first open-source EDA design tools. He also developed a detailed router tool that was bought by several companies. After moving to Silicon Valley he became engineering fellow at Compass Design Automation. In 1997 Patrick joined the startup Magma Design Automation, where he worked on the architecture and implementation of Magma's flagship physical synthesis tools. In 2001 he moved back to Holland to become a full professor in Electrical Engineering at Eindhoven University. In 2005, Patrick and his family decided to return back to Silicon Valley to rejoin Magma Design Automation as Chief Technologist. After the acquisition Patrick is scientist at Synopsys working on Physical Synthesis problems. Patrick was chair of ISPD and the 2012 Design Automation Conference. In his spare time he enjoys being with his family, flying a Cessna 172, reading useless information, running, doing projects around the house and listening to hate-radio as well as opera music.
  • Speaker: Cyro Hemsi
  • Institution: Keysight Technologies
  • Subject: Caracterização de dispositivos semicondutores - visão geral e exemplos práticos com B1500A
  • Local: UFRGS - INF - CEI (Building 43424) - Auditorium Prof. Castilho
  • Abstract: Esta palestra apresenta uma introdução a testes paramétricos de semicondutores, descrevendo os principais testes IxV, CxV, pulsados, testes de reliability e Ruído, o hardware de medida necessário e alguns exemplos, ainda incluindo técnicas de medição que permitem atingir “fA” e “nV”.
  • Short Bio: Cyro Hemsi é atualmente engenheiro de aplicações na Keysight Technologies. Graduado em Engenharia Elétrica pela Unicamp e Mestre em Telecomunicações pela Poli/USP, possui vasta experiência em áreas de eletrônica e telecomunicações, com passagens por empresas como Promon, Ericsson e ZTE.
  • Speaker: Roberto Murphy
  • Institution: INAOE, Mexico
  • Subject: Characterization of the MOS Transistor in the High-Frequency Regime
  • Local: UFRGS - INF - CEI (Building 43424) - Auditorium Prof. Castilho
  • Abstract: "The MOS transistor is the basis for most of modern day integrated circuits. Furthermore, as the technological node has been scaled down, MOS operating frequency has dramatically increased, opening the door to a wide variety of high- frequency applications, reaching cut-off frequencies of the order of several hundreds of Gigahertz. Circuit and system applications employing wireless communications are used nowadays for a wide variety of applications, and the trend clearly shows that these types of circuits will be needed for a host of novel applications in the years to come. This lecture spans the fundamental aspects of bulk MOS transistor characterization in the high-frequency regime, covering key aspects such as set-up calibration, measurements and de-embedding techniques, to continue with the underlying physics, modeling and data reduction. The discussion is limited to the bulk MOS transistor, for which the most important aspects are discussed, from substrate effects, parasitic elements, intrinsic behavior, geometrical considerations and future perspectives both in device fabrication and measurements."
  • Short Bio: Roberto S. Murphy-Arteaga (M´92, SM´02) received his B.Sc. degree in Physics from St. John’s University, Minnesota, and got his M.Sc. and Ph.D. degrees from the National Institute for Research on Astrophysics, Optics and Electronics (INAOE), in Tonantzintla, Puebla, México. He has taught graduate courses at the INAOE since 1988, totaling over 110 taught undergrad and graduate courses. He has given 90 talks at scientific conferences and directed seven Ph.D. theses, 15 M.Sc. and 2 B.Sc. theses. He has published more than 120 articles in scientific journals, conference proceedings and newspapers, and is the author of a text book on Electromagnetic Theory. He is currently a senior researcher with the Microelectronics Laboratory. Dr. Murphy’s research interests are the physics, modeling and characterization of the MOS Transistor and passive components for high frequency applications, especially for CMOS wireless circuits, and antenna design. He is a Senior Member of IEEE, a Distinguished Lecturer of the Electron Devices Society, the President of ISTEC, a member of the Mexican Academy of Sciences, and a member of the Mexican National System of Researchers (SNI).
  • SIM 1
  • Chair: Marcelo Johann (UFRGS)
  • Subject: Session I - Electronic Design Automation I
  • Local: UFRGS - INF - Convention Center (Building 43413) - Lower Auditorium
    • 4:00PM – 4:15PM / Logic Minimization by Gate Merging
      Luciana Mendes Da Silva, Calebe Micael de Oliveira Conceição, Guilherme Bontorin and Ricardo Reis
    • 4:15PM – 4:30PM / Logic Synthesis for Emerging Technologies Based on FPGA Technology Mapping
      Augusto Neutzling, Jody Maick Matos, Andre Reis and Renato Ribas
    • 4:30PM – 4:45PM / An Academic Exploratory Tool for Global Placement
      Gabriel Porto, Antonino B. Pereira, Paulo F. Butzen and Cristina Meinhardt
    • 4:45PM – 5:00PM / Synthesis of Material Implication Expressions from Sum-of- Products
      Felipe Marranghello, Vinicius Callegaro, Andre Reis and Renato Ribas
  • SIM 2
  • Chair: Paulo Butzen (FURG)
  • Subject: Session II - Digital Design I
  • Local: UFRGS - INF - Convention Center (Building 43413) - Upper Auditorium
    • 4:00PM – 4:15PM / Synthesis of an Organ Audio Sampler Prototype in 180nm CMOS VLSI
      Josias Diego Martins and Sergio Bampi
    • 4:15PM – 4:30PM / A Modular DCT Architecture for the HEVC Supporting Multiple Block Sizes
      Jones Goebel, Guilherme Paim, Luciano Agostini, Bruno Zatt and Marcelo Porto
    • 4:30PM – 4:45PM / XOR Logic Gates: PVT Variability Impact on Performance at 32nm
      Fabio Gustavo Rossato Gomes Silva, Cristina Meinhardt and Paulo Francisco Butzen
    • 4:45PM – 5:00PM /Hash Indexes Hardware Architechture for the Hash Based Intra Block Copy
      João Barth, Luan Audibert, Bruno Zatt, Marcelo Porto and Luciano Agostini
  • SIM 3
  • Chair: Rafael Soares (UFPEL)
  • Subject: Session III - Embedded Systems I
  • Local: UFRGS - INF - CEI (Building 43424) - Auditorium Prof. Castilho
    • 4:00PM – 4:15PM / Hardware Solution in FPGA for Image Acquisition of Metallic Surfaces
      Valquiria Huttner, Cristiano Steffens, Bruno Leonardo, Vagner Rosa and Silvia Botelho
    • 4:15PM – 4:30PM / Test Zone Search Architecture for High-Definition Quality HEVC Encoding
      Brunno Abreu, Mateus Grellert and Sergio Bampi
    • 4:30PM – 4:45PM / Cache-Aware Profling for HEVC Encoders
      Ana Clara Mativi de Souza, Eduarda Monteiro and Sergio Bampi
    • 4:45PM – 5:00PM / Replacing a Scratchpad SRAM memory by a Scratchpad STT-RAM
      Lisandro Silva, Lizandro Oliveira, Júlio Mattos and Lisane Brisolara
  • Speaker: Alkiviadis Hatzopoulos - AUTh, Greece
  • Institution: AUTh, Greece
  • Subject: Analog Testing and Modeling
  • Local: UFRGS - INF - CEI (Building 43424) - Auditorium Prof. Castilho
  • Abstract: This presentation will include three parts: (a) Wavelet-based Mixed-Signal Testing Using Supply Current Measurements, (b) 3D integrated circuits modeling and testing (Closed-Form Expressions for the Coupling Capacitance and Inductance between Through-Silicon VIA (TSV) Arrays, Modeling and Analysis of Cracked and Void Hole Defected TSV Interconnections) and (c) Substrate and interconnection modeling for frequencies from DC up to 100 GHz.
  • Short Bio: Alkiviadis Hatzopoulos was born in Thessaloniki, Greece. He received his Degree in Physics (with honours), his Master Degree in Electronics and his Ph.D. Degree in Electrical Engineering from the Aristotle University of Thessaloniki, Greece, in 1980, 1983 and 1989 respectively. He was a research associate in the Department of Electrical and Computer Engineering at the Aristotle University of Thessaloniki for seven years and in 1989 he was elected as a Lecturer. Since 2002 he has been elected as the Director of the Electronics Laboratory. Dr. Hatzopoulos is a member of the Greek Physics Society and the Greek Computer Society. He is also a Senior member of IEEE and elected as IEEE Greece CASS-SSCS Chapter Speaker. He has served as session Speakerman in IEEE conferences and he organised a special session on Testing analog and mixed-signal circuits in the IEEE Int. Conf. on Electronics, Circuits & Systems, ICECS ’96, Rhodes, Greece, Oct. 1996. He has been a visiting Professor at Michigan State University, MI, USA, (Feb. – July 1995) and also a visiting Professor at the Katholieke Universiteit Leuven, Belgium (Feb. – July 2004). Prof. Hatzopoulos is actively involved in educational and research projects and he is the author or co-author of about 140 scientific papers in international journals and conference proceedings. His research interests include: computer-aided circuit design, design and fault diagnosis of integrated circuits and systems (analog, mixed-signal, RF), 3D integrated circuits, analog signal processing, circuit design, electronic communication circuits, instrumentation electronics, substrate noise modelling, Thin-Film-Transistor circuits and Floating-gate transistor applications.
  • Pocket show: Tan Tangos by Hique Gomez & Dúnia Elias
  • Local: UFRGS - INF - Convention Center (Building 43413) - Auditorium

Friday, May 13


  • Local: UFRGS - INF - Convention Center (Building 43413) - Main Lobby
  • Speaker: Gilson Wirth
  • Institution: UFRGS, Brazil
  • Subject: MOS Manufacturing Process
  • Local: UFRGS - INF - Convention Center (Building 43413) - Lower Auditorium
  • Abstract: Serão abordados tópicos introdutórios sobre o processo de fabricação de circuitos e dispositivos MOS, bem como será discutida a operação elétrica do MOSFET, incluindo a discussão das curvas corrente versus tensão (I x V), as regiões de operações e os modelos elétricos básicos.
  • Short Bio: Gilson I. Wirth received the B.S.E.E and M.Sc. degrees from the Universidade Federal do Rio Grande do Sul, Brazil, in 1990 and 1994, respectively. In 1999 he received the Dr.-Ing. degree in Electrical Engineering from the University of Dortmund, Dortmund, Germany. He is currently a professor at the Electrical Engineering Department at the Universidade Federal do Rio Grande do Sul - UFRGS (since January 2007). From 2000 to 2002 he worked as lecturer and researcher in the field of microelectronics at the Informatics Institute, Universidade Federal do Rio Grande do Sul (UFRGS). From July 2002 to December 2006 he was professor and head of the Computer Engineering Department, Universidade Estadual do Rio Grande do Sul (UERGS). He founded the research group in micro- and nano-electronics at UERGS. In July, August and December 2001 he was at Motorola, Austin, Texas, leading the team working in CMOS process technology transfer to CEITEC, Porto Alegre, Brazil. The technology transfer was funded by FAPERGS under grant number 01/1093.3 (first phase of technology transfer) and 01/1628.9 (second phase of technology transfer). In February and March 2002 he was at the Corporate Research Department of Infineon Technologies, Munich, Germany, working as guest researcher on low-frequency noise in deep submicron MOS devices. His research work is focused on reliability and yield of MOS devices and circuits, including low-frequency noise, bias temperature instability (BTI), radiation effects, and design techniques to improve yield and reliability.
  • Speaker: Eduardo da Silva
  • Institution: UFRJ, Brazil
  • Subject: The Future of 3D Imaging: Plenoptic Functions and Light Fields
  • Local: UFRGS - INF - Convention Center (Building 43413) - Lower Auditorium
  • Abstract: This talk starts with a brief review of 3D processing and perception. Then, it defines the plenoptic function, a 7-dimensional function that is able to represent all the visual information in the world. This is followed by the analysis of simplifications to the plenoptic function, such as pinhole cameras, multiview video, video-plus-depth representations, point clouds and light fields. Going in the direction of practical applications, light field cameras are described, and refocusing techniques using light fields are analyzed, highlighting the richness and power of the plenoptic representation. The talk ends with a brief review iof the standardization activities in the area of plenoptic imaging.
  • Short Bio: Eduardo A. B. da Silva is a Professor at Universidade Federal do Rio de Janeiro since 1989. He is co-author of the book "Digital Signal Processing - System Analysis and Design", Cambridge University Press, with editions in 2002 and 2010, that has been translated to Portuguese and Chinese. He has served as associate editor of the IEEE Transactions on Circuits and Systems - Part I, in 2002, 2003, 2008 and 2009, of the IEEE Transactions on Circuits and Systems - Part II in 2006 and 2007, and of Multidimensional, Systems and Signal Processing, Springer since 2006. He is Deputy Editor in Chief of the IEEE Transactions on Circuits and Systems I: Regular Papers. He is Vice-President of Regional and Membership Activities of the IEEE Circuits and Systems Society since 2014, and has been a member of its Board of Governors in 2012 and 2013. He was also a member of the IEEE Publications Services and Products Board Strategic Planning Committee since 2013. His research interests lie in the fields of digital signal and image processing, especially signal compression, digital television, wavelet transforms, and applications to telecommunications and the oil and gas industry.
  • Speaker: Sérgio Bampi
  • Institution: UFRGS/Embrasul
  • Subject: Power Quality Monitoring System with Data Compression: System Architecture and ASIC Design
  • Local: UFRGS - INF - Convention Center (Building 43413) - Lower Auditorium
  • Abstract: Power quality analyzers (PQA) are data acquisition/processing/communication equipments used to evaluate AC power line parameters. The evaluation of these parameters is essential in industrial environments. This talk describes the requirements and system level design of a PQA developed and manufactured by Embrasul – the RE8000, which is internationally certified as class “A” under IEC 61000-4-30 standard requirements. The talk will describe the design and the ASIC implementation of a data compression/decompression (CODECPQ-CI) core developed for the PQA . The ASIC co-processes with FPGA and OMAP cores, and its coding/decoding functionalities bring a very substantial increase in data storage capabilities. The architecture of the CODEC core is presented as well as the functional verification and physical design strategy used in the chip design. The ASIC compresses 4K words of measured data (in IEEE754 SP floating point) in 10 to 15 ms, while reaching average compression ratios of 20X, with up to 100X ratio at peaks. The CODECPQ-CI occupies 15mm2 in CMOS 130nm, including 400K area-equivalent gates, and 10 dedicated SRAM memory blocks. The chip was fabricated by X-FAB and is under system-level bring-up test.
  • Short Bio: Sergio Bampi received the B.Sc in Electronics Engineering and the B.Sc. in Physics from the Federal Univ. of Rio Grande do Sul (UFRGS, 1979), Brazil, and the M.Sc. and Ph.D. degrees in EE from Stanford University (USA) in 1986. Full professor in the Architecture and Microelectronics fields at the Informatics Institute (UFRGS). He directs research in the Microelectronics and Computer Science Programs at UFRGS since 1987. He served as the technical director of the Microelectronics Center CEITEC (2005-2008) and is the past President of the FAPERGS Research Funding Foundation and of the SBMICRO Society (2002-2004). His research interests are in the area of IC design, nano-CMOS devices, mixed signal and RF CMOS design, low power digital design, dedicated complex algorithms, architectures, and ASICs for image and video processing. He has co-authored more than 200 papers in these fields and in MOS devices and EDA. He is a member of IEEE, ACM, SBMICRO scientific societies. He was the Distinguished Lecturer or IEEE CAS 2010-2011,Technical Program Speaker of IEEE SBCCI Symposium (1997, 2005), SBMICRO (1989, 1995), IEEE LASCAS (2013), VARI 2016 Workshop, and track Speaker of several conferences.
  • Speaker: Victor Grimblatt - Synopsys, Chile
  • Institution:Synopsys, Chile
  • Subject: At the Dawn of Industry 4.0 – Design Makes Everything Different
  • Local: UFRGS - INF - Convention Center (Building 43413) - Lower Auditorium
  • Abstract: Technology is changing the world, IoT and IoE are new concepts that are changing the way we communicate, work and entertain. These new technologies are also impacting the industry creating a new revolution on the way we produce goods and services. Industry 4.0 will change dramatically current industry paradigms. This talk will explain the different industry revolutions since the XIX century, it will also cover in detail what is Industry 4.0 and how electronics and EDA are at the core of this new revolution. Finally the talk will explain how an IoT device is designed and how IP is helping on this design.
  • Short Bio: Victor Grimblatt was born in Viña del Mar, Chile. He has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is currently R&D Group Director and General Manager of Synopsys Chile, leader in Electronic Design Automation (EDA). He opened the Synopsys Chile R&D Center in 2006. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore he is often consulted for new technological business development. Before joining Synopsys he worked for different Chilean and multinational companies, such as Motorola Semiconductors, Honeywell Bull, VLSI technology Inc., and Compass Design Automation Inc. He started to work in EDA in 1988 in VLSI Technology Inc. where he developed synthesis tools being one of the pioneers of this new technology. He also worked in embedded systems development in Motorola semiconductors. In 1990 he was invited by professor McCluskey to present his work in Logic Synthesis at the CRC – Stanford University. He has published several papers in EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, and Embedded Systems. From 2006 to 2008 he was member of the “Chilean Offshoring Committee” organized by the Minister of Economy of Chile. In 2010 he was awarded as “Innovator of the Year in Services Export”. In 2012 he was nominated to best engineer of Chile. He is also member of several Technical Program Committees on Circuit Design and Embedded Systems. Since 2012 he is Speaker of the IEEE Chilean chapter of the CASS. Victor Grimblatt is from 2002 professor of Electronics and IC Design in Universidad de Chile and Universidad de los Andes.
  • SIM 4
  • Chair: Fernando Moraes (PUCRS)
  • Subject: Session IV - Electronic Design Automation II
  • Local: UFRGS - INF - Convention Center (Building 43413) - Lower Auditorium
    • 4:00PM – 4:15PM / Drive Strength Aware Cell Movement Techniques for Timing Driven Placement
      Mateus Fogaça, Guilherme Flach, Jucemar Monteiro, Marcelo Johann and Ricardo Reis
    • 4:15PM – 4:30PM / Automatic Design of a Telescopic Amplifier Based on Particle Swarm Optimization
      Robson Domanski, Alessandro Girardi and Anderson Fortes
    • 4:30PM – 4:45PM / A PTM Model for Stuck-Open Faults in Combinational Logic Gates
      Rafael Schivittz, Cristina Meinhardt and Paulo F. Butzen
    • 4:45PM – 7:00PM / Reliability Evaluation of Combinational Circuits from a Standard Cell Library
      Ygor Quadros De Aguiar, Alexandra Lackmann Zimpeck and Cristina Meinhardt
  • SIM 5
  • Chair: Guilherme Pereira Paim (UFPEL)
  • Subject: Session V - Digital Design II
  • Local: UFRGS - INF - Convention Center (Building 43413) - Upper Auditorium
    • 4:00PM – 4:15PM / A Parallel Hardware Architecture for SAD Calculation on Motion Estimation
      Mateus Melo, Gustavo Smaniotto, Rafael Soares and Marcelo Porto
    • 4:15PM – 4:30PM / A comparative study of 1 bit SRAM topologies
      Roberto Almeida, Paulo Butzen and Cristina Meinhardt
    • 4:30PM – 4:45PM / A New Methodology to Teach Computer Organization and Architecture
      Aline Oliveira Da Silva, Alian Moreira Engroff, Aline Vieira De Mello and Alessandro Girardi
    • 4:45PM – 5:00PM / PVT Variability Evaluation of 1 bit Full Adders
      Ingrid Oliveira, Cristina Meinhardt, Vinicius Zanandrea and Stéphanie Ames
  • SIM 6
  • Chair: Claudio Diniz (UCPEL)
  • Subject: Session VI - Embedded Systems II
  • Local: UFRGS - INF - CEI (Building 43424) - Auditorium Prof. Castilho
    • 4:00PM – 4:15PM / Evaluating the Energy of Power Traces to Improve DPA Attacks
      Rodrigo Lellis and Rafael Soares
    • 4:15PM – 4:30PM / Physical Synthesis of Pampium Microcontroller for Embedded Applications
      Alian Moreira Engroff, Aline Oliveira Da Silva, Cristian Muller, Alessandro Girardi and Paulo Comassetto
    • 4:30PM – 4:45PM / A Local Water Control Architecture based on Internet of Things to Water Supply Crisis
      Sergio Mendonca, João Ferreira, Fábio Bonifácio and Fernanda Alencar
    • 4:45PM – 5:00PM / Evaluating the Costs of Software-based Fault Tolerant Techniques in GPUs
      Marcio Gonçalves, Fernando Brenner and José Rodrigo Azambuja
  • Moderator: Sérgio Bampi - UFRGS, Brazil
  • Institution: TBD
  • Subject: TBD: Present and Future of Microelectronics in Latin America
  • Local: UFRGS - INF - Convention Center (Building 43413) - Lower Auditorium
  • Abstract: TBD
  • Short Bio: TBD
  • Unitec Semicondutores, Brasil
  • Panelist: Edelweiss Ritt
  • Short Bio: Director of Product Development
  • Synopsys, Chile
  • Panelist: Victor Grimblatt
  • Short Bio: R&D Group Director and General Manager
  • HT Micron Semicondutores, Brasil
  • Panelist: Leandro Profes
  • Short Bio: Strategic Marketing and Business Development Manager
  • CEITEC, Brasil
  • Panelist: TBD
  • Short Bio: TBD

Saturday, May 14


  • Local: UFRGS - INF - CEI (Building 43424) - Main Lobby
  • Speaker: Hamilton Klimach
  • Institution: UFRGS, Brazil
  • Subject: Circuitos Integrados Analógicos MOS - Características, Necessidades e Desafios
  • Local: UFRGS - INF - CEI (Building 43424) - Auditorium Prof. Castilho
  • Abstract: Desde o surgimento dos primeiros dispositivos e circuitos eletrônicos há quase um século, os sistemas eletrônicos têm evoluído rapidamente, ocupando cada vez mais espaço, até o momento atual onde a eletrônica permeia praticamente todas as atividades humanas. Embora em certa fase deste desenvolvimento os sistemas de processamento digital tenham passado a exercer um papel fundamental, os sistemas analógicos (e de rádio-frequência) continuam imprescindíveis em diversas funções, e seu contínuo desenvolvimento, utilizando novas tecnologias e restrições, tem se mostrado um grande desafio à indústria de semicondutores. Nesta palestra serão discutidos a evolução e os aspectos relevantes que desafiam os projetistas no desenvolvimento dos circuitos analógicos atuais e das suas próximas gerações.
  • Short Bio: Hamilton Klimach received the B.Eng. and M.Sc. degrees in electrical engineering from the Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1988 and 1994, respectively, and the Dr.Eng. degree in Electrical Engineering from the Federal University of Santa Catarina (UFSC), Florianopolis, Brazil, in 2008. From 1989 to 1990 he was with EDISA/HP, working as a hardware computer designer. Since 1990 he is a Professor at the Electrical Engineering Department of Federal University of Rio Grande do Sul, where he was the Head of the Department from 2010 to 2011, and a Dr.Eng. and M.Sc. advisor in the Microelectronics Graduate Program (PGMicro) in the same university. He is also working in the AMS/RF branch of the IC-Brazil Program since 2009. His research interests are in analog, mixed-signal and RF IC design, and in semiconductor device and variability modeling. He is a member of the IEEE Circuits and Systems Society.
  • Speaker: Eduardo Lima
  • Institution: UFPR, Brasil
  • Subject: Ferramentas computacionais para análise e projeto de circuitos RF
  • Local: UFRGS - INF - CEI (Building 43424) - Auditorium Prof. Castilho
  • Abstract:O projeto de circuitos RF demanda por simulações numéricas que impõem severas restrições aos métodos tradicionais em circuitos analógicos. Nesse contexto, simuladores dedicados ao projeto de circuitos RF oferecem ao projetista um conjunto de ambientes de simulação adequados às particularidades destes circuitos. Esta palestra discutirá as principais ferramentas computacionais de análise e projeto de circuitos RF, com destaque para a simulação de parâmetros S, as técnicas de estado estacionário periódico (equilíbrio harmônico e método do tiro) e os métodos de envoltória. Serão abordados os fundamentos básicos e as limitações de cada técnica, com o objetivo de auxiliar no correto uso do ambiente de simulação, bem como na interpretação crítica acerca da validade dos resultados obtidos. Exemplos de aplicação das diferentes técnicas serão também apresentados.
  • Short Bio:Eduardo Gonçalves de Lima received the B.Sc. degree in electrical engineering from Politecnico di Torino, Turin, Italy, in 2004, and from Universidade Estadual de Campinas, Brazil, in 2005, and the Ph.D. degree in electronic devices from Politecnico di Torino in 2009. Since 2010 he is an Assistant Professor at the Department of Electrical Engineering of Federal University of Paraná. His research interests are behavioral modeling and digital baseband pre-distortion of RF power amplifiers.
  • SIM 7
  • Chair: Alessandro Girardi (Unipampa)
  • Subject: Session VII - Analog Design
  • Local: UFRGS - INF - CEI (Building 43424) - Auditorium Prof. Castilho
    • 12:00PM – 12:15PM / Complexity-reduced Polynomial Approximations with Memory based on the Orthogonal Least Squares
      Luis Schuartz and Eduardo Lima
    • 12:15PM – 12:30PM / Improved 2D Memory Polynomial Model for the Digital Baseband Predistortion of Dual-band RF PAs
      Otávio Riba and Eduardo Lima
    • 12:30PM – 12:45PM / A Reconfigurable Operational Transconductance Amplifier in 180 nm Technology
      Mateus C. S. Oliveira, Paulo de Aguirre, Lucas Compassi Severo and Alessandro Girardi
    • 12:45PM – 1:00PM / Polynomial and Filtering for the Reduction of Peak-to- Average Power Ratio in Wireless Transmitters
      Leandro Silva and Eduardo Lima
    • 1:00PM - 1:15PM / Analysis on the Linear Procedure for the Parameter Identification of RF PA Rational Model with Memory
      Victor Francisco and Eduardo Lima
    • 1:15PM - 1:30PM / Decomposed Piecewise Look-up Table-based Memory Polynomial Model for RF Power Amplifiers
      André Zanella and Eduardo Lima
  • SIM 8
  • Chair: Luiz Fernando Ferreira (UFRGS)
  • Subject: Session VIII - Emerging Technologies
  • Local: UFRGS - INF - Library (Building 43412) - Auditorium 0
    • 12:00PM – 12:15PM / Deposition influence in electric and morphologic behavior of integrated circuits metallic lines edited by focused ion beam
      Saulo Jacobsen, Emmanuel Petitprez, Ronald Tararam, Cristiano Krug and Marcelo Lubaszewski
    • 12:15PM – 12:30PM / Investigating SET effects on FinFET circuits
      Giane Ulloa, Samuel Toledo and Cristina Meinhardt
    • 12:30PM – 12:45PM / Electrical Evaluation of Complex Logic Functions Implemented With Independent-Gate FinFET
      Andres Mauricio Asprilla Valdes, Vinicius Possani, Felipe Marranghello, Andre Reis and Renato Ribas
    • 12:45PM – 1:00PM / Design of Full Adders on MIGFET Devices
      Jeferson José Baqueta, Vinicius Neves Possani, André Inácio Reis and Renato Perez Ribas
  • Speaker: Organization
  • Subject: Closing Session
  • Local: UFRGS - INF - CEI (Building 43424) - Auditorium Prof. Castilho
  • Local: Riversides Shikki Restaurant - Av. Nilo Peçanha, 1766


General Chair:
Raphael Brum, UFRGS
Ricardo Reis, UFRGS
EMicro Program Chairs:
Fernando Moraes, PUCRS
Paulo César Comassetto de Aguire, Unipampa
SIM Program Chairs:
Cristina Meinhardt, FURG
José Azambuja, FURG
Local Chair:
Carolina Metzler, UFRGS
Finance Chair:
Alexandra L. Zimpeck, UFRGS
IEEE CASS Liaison:
Ricardo Reis, UFRGS


Universidade Federal do Rio Grande do Sul - Instituto de Informática
Anfiteatro do Centro de Eventos, prédio 43413 (antigo 67)
Campus do Vale, Porto Alegre - Rio Grande do Sul, Brazil.