Ultra-low power logic circuits: From voltage-mode to current-mode Massimo Alioto Abstract In this invited talk, a survey of recent design techniques for ultra-low power logic circuits is presented. Traditional voltage-mode logic styles are discussed, and their limitations in subthreshold regime are highlighted. The effect of interdie and intradie process variations is analyzed, and simple models to predict the effect on energy/delay variations are presented. Current-mode logic styles are then analyzed, and their advantages in terms of minimum energy per operation are discussed. The benefits of the decoupling of energy consumption and supply voltage are widely described along with the advantages that are gained in practical implementations. Clear guidelines to design ultra-low power standard cell libraries are also derived. Models in nanometer CMOS technologies are presented and used to derive clear design guidelines and criteria for ultra-low power applications. Techniques to counteract process and temperature variations are discussed at transistor and system level of abstraction, with emphasis on feedback biasing schemes that compensate interdie and temperature variations. Finally, schemes that are able to operate with a large supply voltage uncertainty are described in detail. Short BIO: Massimo Alioto (M’01–SM’07) was born in Brescia, Italy, in 1972. He received the laurea degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, respectively. In 2002, he joined the Dipartimento di Ingegneria dell’Informazione (DII) of the University of Siena as a Research Associate and in the same year as an Assistant Professor. In 2005 he was appointed Associate Professor of Electronics, and was engaged in the same faculty in 2006. In the summer of 2007, he was a Visiting Professor at EPFL ‐ Lausanne (Switzerland). In 2009‐2010, he is Visiting Professor at BWRC – UCBerkeley, investigating on ultra‐low power circuits and wireless sensor nodes. Since 2001 he has been teaching undergraduate and graduate courses on advanced VLSI digital design, microelectronics and basic electronics. He has authored or co‐authored more than 140 publications on journals (50+, mostly IEEE Transactions) and conference proceedings. Two of them are among the 25 most downloaded TVLSI papers in 2007 (respectively 10th and 13th). He is coauthor of the book Model and Design of Bipolar and MOS Current‐Mode Logic: CML, ECL and SCL Digital Circuits (Springer, 2005). His primary research interests include the modeling and the optimized design of CMOS high‐performance, low‐power and ultra low‐power digital circuits, arithmetic and cryptographic circuits, interconnect modeling, design/modeling for variabilitytolerant and low‐leakage VLSI circuits, circuit techniques for emerging technologies. He is the director of the Electronics Lab at University of Siena (site of Arezzo). Prof. Alioto is an IEEE Senior Member and a member of the HiPEAC Network of Excellence. He is the Chair Elect of the “VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society, for which he is also Distinguished Lecturer. He is regularly invited to give talks and tutorials to academic institutions, conferences and companies throughout the world. He has served as a member of various conference technical program committees (ISCAS, PATMOS, ICM, ICCD, CSIE) and Track Chair (ICECS, ISCAS, ICM, ICCD). He serves as Associate Editor of the IEEE Transactions on VLSI Systems, as well as of the Microelectronics Journal, the Integration – The VLSI journal and the Journal of Circuits, Systems, and Computers. He is Guest Editor of the Special Issue “Advances in oscillator analysis and design” of the Journal of Circuits, Systems, and Computers (2009)