Program Schedule
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Monday, March 2nd
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Tuesday, March 3rd
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Wednesday, March 4th
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Thursday, March 5th
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| 08:00 - 08:30 |
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Opening Session |
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| 08:30 - 09:00 |
TTEP Tutorials Registration |
Keynote |
Embedded Tutorial 1 |
Embedded Tutorial 2 |
| 09:00 - 09:30 |
TTEP Tutorial 1 |
| 09:30 - 10:00 |
Corp. Supporter Presentation |
Automatic Test Generation |
Test of Embedded Software,
Protocol and Webs |
| 10:00 - 10:30 |
Coffee-break |
| 10:30 - 11:00 |
Coffee-break |
Test of SoCs and NoCs |
Coffee-break |
Coffee-break |
| 11:00 - 11:30 |
TTEP Tutorial 1 |
Analog and Mixed Signal
Testing and Diagnosis |
Dealing with SEUs and
Radiation Effects |
| 11:30 - 12:00 |
Fault Modelling,
Analysis and Simulation |
| 12:00 - 12:30 |
| 12:30 - 13:00 |
Break for Lunch |
Break for Lunch |
Break for Lunch |
Break for Lunch |
| 13:00 - 13:30 |
| 13:30 - 14:00 |
DFT, BIST |
| 14:00 - 14:30 |
Invited Talk |
Fault Tolerant
Architectures
and Techniques |
| 14:30 - 15:00 |
TTEP Tutorial 2 |
Single-Event Upset Modelling,
Simulation and Detection |
| 15:00 - 15:30 |
Fault Modelling,
Analysis and Diagnosis |
| 15:30 - 16:00 |
Social Event |
Coffee-break |
| 16:00 - 16:30 |
Coffee-break |
Coffee-break |
Process Control
and Measurements |
| 16:30 - 17:00 |
TTEP Tutorial 2 |
Design, Verification/Validation
and Synthesis for Testability |
| 17:00 - 17:30 |
Concluding Remarks |
| 17:30 - 18:00 |
Panel Discussion |
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| 18:00 - 18:30 |
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| 18:30 - 19:30 |
| 20:00 - 23:00 |
Welcome Reception |
Gala Dinner |
Monday, March 2nd
08:30 - 09:00 |
TTEP Tutorials Registration |
09:00 - 10:30 |
TTEP Tutorial 1
Title: "Design, Test, & Yield Implications and Analysis under Parameter Variations"
Speaker: Kaushik ROY - Purdue University (USA) |
10:30 - 11:00 |
Coffee break |
11:00 - 12:30 |
TTEP Tutorial 1
Title: "Design, Test, & Yield Implications and Analysis under Parameter Variations"
Speaker: Kaushik ROY - Purdue University (USA) |
12:30 - 14:30 |
Lunch |
14:00 - 16:00 |
TTEP Tutorial 2
Title: "Design for Manufacturability"
Speaker: Yervant Zorian - Virage Logic Corp., USA |
16:00 - 16:30 |
Coffee Break |
16:30 - 18:00 |
TTEP Tutorial 2
Title: "Design for Manufacturability"
Speaker: Yervant Zorian - Virage Logic Corp., USA |
18:00 - 20:00 |
LATW On-site Registration |
Tuesday, March 3rd
08:00 - 08:20 |
Registration |
08:20 - 08:40 |
Opening Session |
08:40 - 09:30 |
KEYNOTE ADDRESS
Title: “Integration of Design and Test in the Nano - Scale Era: Wishful Thinking or Reality?”
Speaker: Kaushik ROY - Purdue University (USA) |
09:30 - 09:50 |
CORP. SUPPORTER PRESENTATION
The Microelectronics and Embedded Electronics Laboratory: Projects and
Challenges
Lucas Travassos - National Industrial Apprenticeship Service - Bahia Regional Department |
09:50 - 10:20 |
Coffee break |
10:20 - 11:40 |
SESSION 1: Test of SoCs and NoCs
Chair: Hans Wunderlich (University of Stuttgart, Germany)
Measuring Clock - Signal Modulation Efficiency for Systems - on - Chip in Electromagnetic Interference Environment
Jorge SEMIÃO, Judite FREIJEDO, Marlon MORAES, Marcelo MALLMANN, Cláudia ANTUNES, Juliano BENFICA, Fabian VARGAS, Marcelino SANTOS, Isabel C. TEIXEIRA, Juan-Jose RODRÍGUEZ ANDINA, João Paulo TEIXEIRA, Daniel LUPI, Edmundo GATTI, Luís GARCIA, Fernando HERNANDEZ
University of Algarve, IST/ INESC-ID Lisboa - Portugal, PUCRS - Brazil, University of Vigo - Spain, Inst. Nacional de Tec. Industrial (INTI) - Argentina, and Universidad ORT - Uruguay
On - Line Test and Monitoring of Multi - Processor SoCs: A Software - Based Approach
Mounir BENABDENBI, Francois PECHEUX, Etienne FAURE
University Pierre and Marie Curie - France
NoC Interconnection Functional Testing: Using Boundary - Scan to Reduce the Overall Testing Time Marcos HERVÉ, Erika COTA, Fernanda KASTENSMIDT, Marcelo LUBASZEWSKI
Universidade Federal do Rio Grande do Sul - Brazil
A Practical Methodology for Experimental Fault Injection to Test Complex Network - Based Systems
Cristina MENEGOTTO, Taisy WEBER, Raul WEBER
Universidade Federal do Rio Grande do Sul - Brazil |
11:40 - 12:45 |
SESSION 2: Fault Modelling, Analysis and Simulation
Chair: Luigi Carro (UFRGS, Brazil)
A Modern Look at the CMOS Stuck - Open Fault
Victor Hugo CHAMPAC, ROBERTO GÓMEZ, Charles HAWKINS, Jaume SEGURA
National Institute for Astrophysics, Optics and Electronics / INAOE - Mexico, University of New
Mexico - USA and University of Balearic Islands - Spain
Deriving an Electrical Model for Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects
Nicolas HOUARCHE, Alejandro CZUTRO, Mariane COMTE, Piet ENGELKE, Ilia POLIAN, Bernd BECKER, Michel RENOVELL
LIRMM, CNRS/ Univ. Montpellier II - France and Albert-Ludwigs-University - Germany
Study of Radiation Effects on PIN Photodiodes with Deep - Trap Levels Using Computer Modelling
Marcelo CAPPELLETTI, Ariel CEDOLA, Sergio BARON, Guillermo CASAS, Eitel PELTZER Y BLANCÁ
Universidad Nacional de La Plata and Instituto de Física de Líquidos y Sistemas Biológicos
CONICET -UNLP - CIC - Argentina |
12:45 - 14:00 |
Lunch |
14:00 - 14:50 |
INVITED TALK
Title: “Embedded Diagnosis - a Key to Reliable Systems”
Presenter: Hans WUNDERLICH - Universitat Stuttgart (Germany) |
14:50 - 15:55 |
SESSION 3: Fault Modelling, Analysis and Diagnosis
Chair: Yoshio Mita (UT, Japan)
Analyzing the Impact of Simultaneous Switching Noise on the Timing Behavior of CMOS Digital Blocks
Florence AZAIS, Yves BERTRAND, Michel RENOVELL
LIRMM, CNRS/ Univ. Montpellier II - France
Performance Modeling of EFT Systems Performability
Fabio CHICOUT, Erica SOUSA, Carlos ARAÚJO, Paulo MACIEL
Federal University of Pernambuco - Brazil
Exploring Machine Learning Techniques for Fault Localization
Lucilia ARAKI, Luciano ASCARI, Aurora POZO, Silvia VERGILIO
Federal University of Parana - Brazil |
15:55 - 16:25 |
Coffee Break |
16:25 - 17:50 |
SESSION 4: Design, Verification/Validation and Synthesis for Testability
Chair: Letícia Bolzani (PUCRS, Brazil)
(A Case Study for Formal Verification of a Timing Co - Processor
Cristiano RODRIGUES
Freescale Semiconductor - Brazil
High - Level Decision Diagrams Based Coverage Metrics for Verification and Test
Maksim JENIHHIN, Jaan RAIK, Anton CHEPUROV, Uljana REINSALU, Raimund UBAR
Tallin University of Technology - Estonia
Minimization of Incompletely Specified Finite State Machines Based on Distinction Graphs
Alex ALBERTO, Adenilso SIMÃO
Universidade de São Paulo - Brazil
BUGTRACER: A System for Integrated Circuit Development Tracking and Statistics Retrieval
Thiago CARDOSO, José Augusto NACIF, Antonio Otavio FERNANDES, Claudionor COELHO
Universidade Federal de Minas Gerais - Brazil
A Method for HW Functional Verification through HW/SW Co - Simulation in Complex Systems: H.264/AVC Decoder as Case Study
Dieison Antonello DEPRA, Bruno ZATT, Sergio BAMPI
Universidade Federal do Rio Grande do Sul - Brazil |
17:50 - 19:30 |
PANEL DISCUSSION
Title: "VLSI Devices in Space Applications: Challenges and Solutions"
Organizer: Eduardo Bezerra, PUCRS - Brazil
Moderator: Luigi Carro, UFRGS - Brazil
Panelists: Vincent Pouget, IXL - France
Gilson Wirth, UFRGS - Brazil
Raoul Velazco, TIMA - France |
20:00 - 22:00 |
Welcome Reception |
Wednesday, March 4th
08:30 - 09:40 |
EMBEDDED TUTORIAL 1
Title: "Ensuring High Testability Without Degrading Security"
Co - presenters: Marie - Lise FLOTTES, Giorgio DI NATALE - LIRMM (France) |
09:40 - 10:30 |
SESSION 5: Automatic Test Generation
Chair: Maksim Jenihhin (TTU, Estonia)
On the Derivation of a Minimum Test Set in High Quality Transition Testing
Tsuyoshi IWAGAKI, Mineo KANEKO
Japan Advanced Institute of Science and Technology - Japan
Using a Two - Dimensional Fault List for Compact Automatic Test Pattern Generation
Marc MESSING, Andreas GLOWATZ, Friedrich HAPKE, Rolf DRECHSLER
University of Bremen and Mentor Graphics Development GmbH - Germany |
10:30 - 11:00 |
Coffee break |
11:00 - 12:20 |
SESSION 6: Analog and Mixed Signal Testing and Diagnosis
Chair: Florence Azais (LIRMM, France)
Using Mixed - Mode Test Bus Architecture to RF - Based Fault Injection Analysis and EMC Fault Debug
Eduardo R. SILVA, Fabricio COSTA, Frank H. BEHRENS, Remerson S. KICKHOFEL, Ricardo MALTIONE
Freescale Semiconductor - Brazil
Analog Test Bus Architecture for Small Die Size and Limited Pin Count Devices with Internal IPs Testability Emphasis
Eduardo R. SILVA, Fabricio COSTA, Frank H. BEHRENS, Remerson S. KICKHOFEL, Ricardo MALTIONE
Freescale Semiconductor - Brazil
Estimating the Quality of Oscillation Based Test for Detecting Parametric Faults
José PERALTA, Marcelo COSTAMAGNA, Gabriela PERETTI, Eduardo ROMERO, Carlos MARQUÉS
Universidad Tecnológica Nacional and Universidad Nacional de Córdoba - Argentina
Execution Time Reduction of Differential Power Analysis Experiments
Giorgio DI NATALE, Marie - Lise FLOTTES, Bruno ROUZEYRE
Université Montpellier II - France |
12:20 - 13:30 |
Lunch |
13:30 - 14:35 |
SESSION 7: DFT, BIST
Chair: Mounir Benabdenbi (UPMC, France)
Turning JTAG Inside Out for Fast Extended Test Access
Sergei DEVADZE, Artur JUTMAN, Igor ALEKSEJEV, Raimund UBAR
Testonica Lab OU and Tallin University of Technology - Estonia
Using High - level Method In Testing Asynchronous QDI Circuits
Fahime KHORAMNEJAD, Mehrdad Najibi, Hossein Pedram
Amirkabir University of Technology (Tehran Polytechnic) - Iran
Investigations of the Diagnosibility of Digital Networks with BIST
Raimund UBAR, Jaan RAIK, Sergei KOSTIN
Tallin University of Technology - Estonia |
14:35 - 15:15 |
SESSION 08: Single-Event Upset (SEU) Modelling, Simulation and Detection
Chair: Gilson Wirth (UFRGS, Brazil)
Study of SEU Effects in a Turbo Decoder Bit Error Rate
Marta PORTELA - GARCIA, Mario GARCIA - VALDERAS, Celia LOPEZ - ONGIL, Luis ENTRENA, Bruno LESTRIEZ, Luis BERROJO
Carlos III University of Madrid and VLSI Group of Thales Alenia Space - Spain
Pruning Single Event Upset Faults with Petri Nets
Paolo MAISTRI
TIMA Laboratory (Grenoble INP, UJF, CNRS) - France |
15:30 - 18:00 |
Social Event |
20:00 - 23:00 |
Gala Dinner |
Thursday, March 5th
08:30 - 09:40 |
EMBEDDED TUTORIAL 2
Title: "Failure Mechanisms in Deep Sub - Micron Technologies”
Presenter: Vincent POUGET - IMS (France) |
09:40 - 10:35 |
SESSION 09: Test of Embedded Software, Protocol and Webs
Chair: Nacer-Eddine Zergainoh (TIMA, France)
Testing Requirements for an Embedded Operating System: the Exception Handling Case Study
Lucieli BEQUE, Thiago DAI PRA, Erika COTA
Universidade Federal do Rio Grande do Sul - Brazil
Mutation Based Testing of Web Services
Andre SOLINO, Silvia VERGILIO
Federal University of Parana - Brazil
Applying FIRMAMENT to Test the Communication Protocol SCTP under Network Faults
Torgan SIQUEIRA, Bruno FISS, Raul WEBER, Sergio CECHIN, Taisy WEBER
Universidade Federal do Rio Grande do Sul - Brazil |
10:35 - 11:05 |
Coffee break |
11:05 - 12:40 |
SESSION 10: Dealing with SEUs and Radiation Effects
Chair: Lorena Anghel (TIMA, France)
Using Bulk Built - In Current Sensors and Recomputing Techniques to Mitigate Transient Faults in Microprocessors
Franco LEITE, Tiago BALEN, Marcos HERVÉ, Marcelo LUBASZEWSKI, Gilson WIRTH
Universidade Federal do Rio Grande do Sul - Brazil
Using Software Invariants for Dynamic Detection of Transient Errors
Carlos LISBOA, Carmela GRANDO, Alvaro MOREIRA, Luigi CARRO
Universidade Federal do Rio Grande do Sul - Brazil
Measuring the Effectiveness of Symmetric and Asymmetric Transistor Sizing for Single Event Transient Mitigation in CMOS 90nm Technologies
Thiago ASSIS, Fernanda KASTENSMIDT, Gilson WIRTH, Ricardo REIS
Universidade Federal do Rio Grande do Sul - Brazil
Recovery Scheme for Hardening System on Programmable Chips
Cristina MEINHARDT, Ricardo REIS, Massimo VIOLANTE, Matteo SONZA REORDA
Universidade Federal do Rio Grande do Sul - Brazil
Radiation Damage Characterization of Digital Integrated Circuits
Santiago SONDON, Pablo MANDOLESI
Universidad Nacional del Sur - Argentina |
12:40 - 14:00 |
Lunch |
14:00 - 15:30 |
SESSION 11: Fault Tolerant Architectures and Techniques
Chair: Marta Portela Garcia (UC3M, Spain)
Single Element Correction in Sorting Algorithms with Minimum Delay Overhead
Costas ARGYRIDES, Carlos LISBOA, Dhiraj PRADHAN, Luigi CARRO
Department of Computer Science of the University of Bristol- UK and Universidade Federal do
Rio Grande do Sul - Brazil
Fault Tolerance Assessment of PIC Microcontroller Based on Fault Injection
Ashkan EGHBAL, Hamid R. ZARANDI, and Pooria M. YAGHINI
Amirkabir University of Technology (Tehran Polytechnic) - Iran
Generating Non - Uniform Distributions for Fault Injection to Emulate Real Network Behavior in Test Campaigns
Taisy WEBER, Juliano VACARO, Torgan SIQUEIRA, Ingrid JANSCH - PORTO
Universidade Federal do Rio Grande do Sul - Brazil
Test and Qualification of a Fault Tolerant FPGA Based Active Antenna System for Space Applications Pablo FERREYRA, Ezequiel BRAC, Raoul VELAZCO, Carlos MARQUES
Universidad Nacional de Córdoba, Instituto Universitario Aeronáutico -Argentina and
Laboratoire TIMA - France |
15:30 - 16:00 |
Coffee break |
16:00 - 17:10 |
SESSION 12: Process Control and Measurements
Chair: Victor Champac (INAOE, Mexico)
Analyzing Structure - based Techniques for Test Coverage on a J2ME Software Product Line
Liana SILVA, Sérgio SOARES
University of Pernambuco - Brazil
NBTI - Aware Technique for Transistor Sizing of High - Performance CMOS Gates
Mauricio BANASZESKI DA SILVA, Vinícius VALDUGA DE ALMEIDA CAMARGO, Lucas BRUSAMARELLO, Gilson WIRTH, Roberto da SILVA
Universidade Federal do Rio Grande do Sul - Brazil
Measurement and Control for Risk - based Test Cases and Activities
Ellen SOUZA, Cristine GUSMÃO, Keldjan ALVES, Júlio VENÂNCIO, Renata MELO
Department of Systems and Computing at Pernambuco University - Brazil
Adaptive Position Digital Control with Deadbeat Response for a Platform on a Mobile Vehicle
Harold Rene CHAMORRO VERA, Catalina BUSTOS GONZALEZ, Leandro LOPEZ SANCHEZ
Universidad Distrital Bogotá - Colombia |
17:10 - 17:30 |
Concluding Remarks |
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