Tittle:Integration of Design and Test in the Nano-Scale Era: Wishful Thinking or Reality?
Presenter: Kaushik Roy (Purdue University, USA)
Abstract: The test community have been talking about integration of design and test for the last several years. However, the design and test issues have been dealt with relatively independently so far. Unfortunately, for the sub-90nm technologies, test cost has been skyrocketing and some of the new low power design techniques can have an adverse impact on yield. Hence, the need for the integration of design and test is more than ever. In this talk I will present different test and design methodologies suitable for the nano-scale era and explore self-tuning and self healing techniques for improved yield.

Tittle: Embedded Diagnosis - a Key to Reliable Systems
Presenter: Hans-Joachim Wunderlich (University of Stuttgart, Germany)
Abstract: Design errors, defects during manufacturing, and failures in the complete life cycle of a microelectronic device impact reliability. The talk will discuss how reliability has to be established as a design goal in electronic design automation tols, and how reliability prediction may guide a top down design flow. Failure analysis has to provide sufficient quantitative and qualitative data for such a process. The widespread business model based on fabless companies and outsourcing makes data collection rather complex. For automotive microelectronics, the situation is even more difficult as the very lean production and the very long supply chain make diagnosis an especially time consuming and expensive task with many partners involved. The talk will discuss how self-test and embedded diagnosis features introduce added value for the end customer to increase reliability and to cut down cost.

Tittle:Failure mechanisms in deep sub-micron technologies
Presenter: Vincent Pouget (IMS, France)
Abstract: Using recent semiconductor technologies in applications that require a high level of reliability may present serious risks in terms of premature failure. Indeed, the life time of standard modern digital devices sometimes does not exceed a few years, when demanding applications like space, energy, or automotive require much longer times of operation. The tutorial will review the multiple physical failure mechanisms (like NBTI, HCI, TDDB, SEE...) that can affect the reliability of recent semiconductor devices. For each mechanism, the physical and electrical models will be presented as well as typical characterization methods, and the possible implications for design and test will be discussed.


Tittle:Ensuring high testability without degrading security
Co-presenter: Marie-Lise Flottes, Giorgio Di Natale (LIRMM, France)
Abstract: Cryptographic algorithms are used to protect sensitive information from untrusted parties when the communication medium is not secure. Many secure systems such as smartcards include hardware implementation of symmetric cryptographic algorithms such as (Triple) Data Encryption Standard and Advanced Encryption Standard. The secret keys used to encrypt the data with these algorithms are large enough to prevent any brute force attack that consists in exploring the whole solution space (2^n with 128<n<256). However, the hardware implementation of these cryptographic algorithms allows the hackers to measure the observable characteristics of the physical implementation and deduce the secret key (side-channel attacks). The key can even be discovered by applying a side-channel attack on scan chains. These scan chains, which aim to provide full controllability and observability of internal states, represent nevertheless the most popular design-for-testability scheme. Because crypto-processors and others cores in a secure system must pass through high-quality test procedures to ensure that data are correctly processed, testing of crypto chips faces a dilemma: how to develop a design-for-testability scheme that provides high testability (high controllability and observability) while maintaining high security (minimal controllability and observability)? This tutorial presents the security weaknesses generated by scan designs on hardware AES and DES implementations. It also discusses the pros and cons of security-dedicated DFT and BIST solutions taken from the literature.