TTEP Tutorials


TTEP Tutorial 1

Tittle: Design, Test, & Yield Implications and Analysis under Parameter Variations
Presenter: Kaushik Roy (Purdue University, USA)
Abstract: In sub-65nm regime, parameter variations have become increasingly important and can affect yield of integrated circuits severely. The minimum geometry transistors, especially in memories, can lead to new variation induced failures. In the first part of the tutorial, we will classify different parameter variations -- die-to-die and within-die -- and will consider the impact of variations and corresponding failures in memories. Techniques to improve memory tests to catch such process variation induced failures will be discussed and self-tuning and self-repairing techniques to improve yield will be considered. In the second part of the tutorial, we will consider both logic and signal processing systems under parameter variations and discuss test and yield improvement techniques using sensors that senses the process corner that the chip is in, and provide corrective action. Test and validation of such systems with sensors and self-tuning features will be considered.


TTEP Tutorial 2

Tittle: Design for Manufacturability
Presenter: Yervant Zorian (Virage Logic Corp., USA)
Abstract: In addition to designing the functionality, today's SOC necessitates designing for manufacturability, yield and reliability. Such requirements are fundamentally transforming the current SoC design methodology. Techniques for enhancing manufacturability, yield, and reliability include yield enhancement techniques, resolution enhancement techniques, new or restricted design rules, variability-aware design, and the addition of a special family of embedded IP blocks, called Infrastructure IP blocks. The latter blocks are meant to ensure manufacturability of the SOC and to achieve adequate levels of yield and reliability. The Infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This tutorial analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of the above techniques. Then, it concentrates on several examples of each of these techniques.