Exact Benchmarks

Benchmarks are essential to support the evolution of EDA environments. Usually, different methods are compared through reference circuits, allowing their relative performance analysis. However, such an assessment does not indicate how the obtained solutions are far from the optimal circuit building. A novel benchmark suite with known exact solution is presented for the logic synthesis design process. Those benchmark circuits have been synthesized on FPGA and ASIC design flows, showing that there is a room for further improvement on IC design tools.


SwitchCraft environment provides a set of tools for switch network generation. Estimators for delay, area and Power dissipation (dynamic and leakage) are available.

Available soon!

Karma 3 (KARnaugh MAps - Logic Synthesis - Quine-McCluskey algorithm) is a set of logic synthesis tools including Karnaugh maps, Quine-McCluskey minimization, BDDs, probabilities, teaching module and more!

Java Applet
Desktop Version (Full version) 


Logic2Logic is a tool to convert Boolean functions to different formats of representation (truth table, expression, BLIF, terms, BDD, factorized expression, integer). It includes options to compare and visualize functions.

Java Applet
Destop Version (Full version)

Logic-Physical-Aware Benchmark Suite

The Logic-Physical-Aware Benchmark Suite enables to jointly consider logic synthesis and physical design. From educational and benchmarking standpoints, this benchmark suite is intended to break the barrier between logic synthesis and physical design. (read more...)


Simple Flow

Simple Flow is a logic synthesis tool intended to provide a front-end environment addressing simplified versions of synthesis tasks. This current release is based on a synthesis approach targeting a minimal logic network comprised only of simple cells. (read more...)



CDF CellPlex - Automatic logic gate layout generation

Avaiable soon!

Some CAD tools have been developed by the LogiCS team in the last years. The first versions of such tools were created in the scope of LAGARTO (LAyout GenerAtoR TOols) project, in 2000. Since 2005, the R&D agreement between UFRGS and Nangate S/A has also contributed significantly to this effort.



ELIS (Environment for Logic Synthesis)

The ELIS tool is a compilation of several logic synthesis methods, like SIS tool from Berkeley, operating over an unified data structure representing the circuits. Differently from SIS tool, the ELIS one provides a library-free technology mapping generating the CMOS transistor arrangement.

Windows binary and complementary files