Advanced Computing Platforms for Avionics Applications

On the early 2000’s, avionics systems started to be employed as integrated software modules embedded in a same hardware, as an evolution of previous concept of having a same base hardware with several hardware cards, each one performing a dedicated task. This concept, defined as Integrated Modular Avionics (IMA), was standardized in [1] and brought a consistent improvement on avionics system design. IMA systems rely mostly on Commercial Off-The-Shelf (COTS) hardware, leaving most of dedicated and customized tasks to be performed by software and programmable hardware applications. During the recent years, the IMA concept had broad acceptance on the market, especially in civil avionics area. The foundations of IMA design rely on the determinism of the combination of each application and the hardware over which it is running. Depending on the criticality of the function being implemented by an IMA embedded software application, it is mandatory to know the expected behavior of such implementation in such a way that this application will not interfere on other ones running over the same processor and sharing the same hardware resources [2]. The best way to assure this independence and non-interference between applications running over the same hardware is assuring the temporal and spatial separation between applications [3]. Spatial separation means to assure that each application has its own memory area and this area will not be used by any other application except the one intended to use. Temporal isolation means that a given application will seize the hardware resources to execute only during a given pre-established amount of time and this amount will not be exceeded in order to do not jeopardize the execution of other applications that will run using the same hardware resources. Spatial separation is a goal that does not present big challenges to be achieved, since real-time operating systems (RTOS) compliant with ARINC653 standard [4] offer a robust tool set to assure the isolation of memory areas between applications. However, temporal separation is a much more delicate issue to be dealt with. This happens because in hard real-time applications each task has hard deadlines to meet and the real-time operating system shall manage the scheduler in order to avoid any unexpected and not deterministic behaviors. In order to assure such real time performance the OS needs to know what is the effort, in terms of time consumption, that each software application takes. Such metric, is named as Worst Case Execution Time (WCET).

In other hand, although the introduction of multi-core processors integrated in a single chip (MPSoC) brought many improvements in scalability and power efficiency to computer system, it also posed some challenges compared to single core processors, like the way to perform execution time calculation [5] or even proposing new metrics for system performance analysis [6]. Concerning these aspects, this research group studies alternatives to improve the WCET analysis in order to cope with hardware technology evolution towards the usage of multicore processors. In addition, shared resources, tasks parallelism, memory access latencies and inter-core communication, that increases the analysis difficulty, are also taken into account [7].

[1] Integrated Modular Avionics (IMA) development, guidance and certification considerations, RTCA/DO-297, 2005.

[2] A. Lofwenmark and S. Nadjm-Tehrani, “Challenges in Future Avionic Systems on Multi-core Platforms”, in 2014 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW), 2014, pp 115-119.

[3] R. Weilong and Z. Zhengjun, “Kernel-level Design to Support Partitioning and Hierarchical Real-time Scheduling of ARINC 653 for VxWorks”, in 2014 IEEE 12th International Conference on Dependable, Autonomic and Secure Computing, 2014, pp 388-393.

[4] ARINC Specification 653: Part 1, Avionics Application Software Standard Interface, Required Services, ARINC 653, March, 2006.

[5] C. Luque, M. Moreto, F. J. Cazorla, R. Gioiosa, A. Buyuktosunoglu and M. Valero, “CPU Accounting for Multicore Processors”, in IEEE Transactions on Computers, vol. 61, no. 2, February 2012.

[6] M. Otoom and J. M. Paul. “Multiprocessor Capacity Metric and Analysis”, IEEE Transactions on Computers, vol. 64, no. 11, November 2015.

[7] E.P. Freitas, B. Cozer, C. Ferreira, F.R. Wagner, T. Larsson. A Practical Study on WCET Estimation on Multicore Processors for Avionics Applications. In: Aerospace Technology Congress 2016, 2016, Stockholm. Proceedings of Aerospace Technology Congress 2016, 2016.