Professor: Renato Peres Ribas
Hours: 60 hs
Semesters: First and second semesters
Undergraduate Enrollment: The enrollment must be made as Special Student
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Introduction to system integration in ICs. Systems on Chip – trends; levels of specification and abstraction. MOS Transistors and logic gates in CMOS. Combinational logic ICs. Basic principles of CMOS IC manufacturing processes; geometric and electrical design rules. Rules of technology scaling. Digital Logic styles: full and semi-custom. Static CMOS logic. Dynamic logic. Layout styles. Arithmetic Operators design in CMOS. Sequential circuits design. Flip-flops and registers. Regular CMOS structures design: ALU, sRAM, ROM, datapaths. Methodologies, tools and types of regular structures descriptions.
At the end of the discipline students should be able to understand and perform the basic steps of the digital integrated circuit design in CMOS. The course is focused on the design of VLSI systems in CMOS technology, which are predominant in the implementation of state-of-the-art integrated computer systems. The course introduces design techniques in CMOS digital systems, from the principles of operation of MOS transistors, logic gates, macroblocks and regular structures like RAM, Datapath, Register files, non-volatile memory (ROM, EEPROM). Principles of use of tools for layout, simulation, extraction and electrical behavioral specification will be exercised by the students.
• Introduction of the discipline. Review concepts of system integration in VLSI integrated circuits. Scale Integration.
• Basic semiconductor devices. P-n junction devices. Models. MOS structure.
• Models for electrical capacitors M-I-S. MOS structure. Characteristics and CV model at high and low frequencies.
• MOS transistors (NMOS E-, D-NMOS, PMOS): fabrication process, layout, geometry to electrical correlations.
• MOS transistors II – Models and first and second order effects.
• Electrical SPICE simulation: Models, format, types of analysis.
• NMOS and CMOS performance, features, timing, layout. CMOS inverter static and dynamic response. Noise Margins
• Basic CMOS logic.
• Dynamic response. Sizing of gates, logical effort. Sizing of buffers and digital oscillators.
•Laboratory work with electrical simulation (SPICE-like) and with Spectre simulator.
• Static CMOS logic gates. Dynamic response and scaling of transistors. Electrical effects, timing. Specification in. Lib and. Def
• Power consumption. Electrical models for energy and power in CMOS logic.
•Complex CMOS logic, layout techniques, Euler path.
• Switch and pass-transistor logic.
• Combinational circuit design: full-adder and decoders
• N-bit Adders. Logic/Electric techniques for carry acceleration.
• Parasitics. Models for Wiring and interconnect lines.
• Single-rail dynamic logic: Examples of implementation
• Dual-rail structures: voltage-mode logic
• Dual-rail structures: SSDL, ECDL, …
• Dynamic Logic I. Latches and Flip-Flops
• Dynamic Logic II.
• Register and Memory cells. :Regular structures ROM, EPROM, EEPROM,
• RAM (static and dynamic). Structure. Timing. Pre-load decoding. Sense-amplifier
• Model and Design of a Simple end differential amplifier stage. Example of sense-amplifier
• Analog basic blocks. Current mirror pairs.
• Full custom x standard cell gate array x cell library
• Regular structures. Notions of placement, routing, LVS
Practical exercises and one written, open-book verification.
• Rabaey, Jan. Digital Integrated Circuits, Prentice Hall, 1996.
• Weste, N., Harris, D. Principles of CMOS VLSI Design. Addison-Wesley, 3rd edition, 2004.