Research Groups | Computational Tools for Design of Integrated Circuits and Systems
The goal of the research group in CAD tools for integrated circuit (IC) design is to investigate new models and algorithms related to logic synthesis, technology mapping, switch (transistor) network generation and physical design (layout) in order to optimize performance, power consumption, silicon area and noise immunity. IC design is also a focus of the team as a way to verify and validate methods and tools developed.
- Transistor Network Generation: The main focus is to mix the logic and physical synthesis domains in order to optimize the construction of CMOS logic gates and combinational blocks. Different logic styles, cell topologies and transistor sizing methods are considered. CAD tools are developed to pursue such goal.
- Technology mapping is the step of circuit synthesis in which the building blocks that will be used in the final circuit implementation are chosen. Our research goal is to extend the concept of technology mapping beyond the concept of pre-designed cell libraries to perform technology mapping at the switch level, mapping directly to transistor networks.
- BDD package: We are developing a new BDD package with specific support for switch level operations. This package implements specific support for several tasks related to transistor level implementations.
- Logic Gate Behavior Modeling and Cell Design Techniques: Analytical modeling of single CMOS gate behavior is interesting for the fast estimation of delay and power consumption of digital circuits. Leakage current is also becoming quite important in logic cell power dissipation when sub-micrometer processes are targeted. Estimation tools are usually adopted during the design cycle instead of more accurate but more time expensive electrical simulations. In this sense, we are developing analytical models and CAD tools for digital IC design flow improvement.
- Standard Cell Library and ASIC Design Evaluation: Different CMOS logic styles can provide improvements in terms of electrical behavior and/or layout generation when compared to standard CMOS gates. We investigate the impact of different logic families and library generation strategies on the final quality of ASICs.
Recent Research Projects
- LAGARTO Project – Development of tools for automatic generation of logic cell layout (2001-2005). Financial support: CNPq, CAPES, FAPERGS, UFRGS.
- Nangate Project – Development of analytic models, design techniques and CAD tools for the design of CMOS logic gates and digital circuits. Nangate-UFRGS R&D agreement (2005-2009). Financial support: Nangate A/S, CAPES, CNPq, UFRGS.
Recent Research Results
- Research and Development (R&D) agreement between UFRGS and the Danish company Nangate S/A (since 2005) resulted in the creation of the ‘Nangate-UFRGS Research Lab’, with financial support for scholarships, related activities and infra-structure. Besides that, the ‘Nangate do Brasil S.A.’ was created from such partnership, being installed today in the Entrepreneurship Center for Informatics (CEI) at UFRGS. Such collaboration has also given the opportunity for internships (undergraduate and graduate students) at Nangate both in Denmark and Brazil.