Proposta de Tese de Rafael Billig Tonetto

DEFESA DE PROPOSTA DE TESE

Aluno: Rafael Billig Tonetto
Orientador: Prof. Dr. Gabriel Luca Nazar
Coorientador: Prof. Dr. Antonio Carlos Schneider Beck Filho

Título: Improving Performance, Energy Efficiency and Reliability of Heterogeneous Systems Under Process Variability Constraints
Linha de Pesquisa: Sistemas Embarcados

Data: 10/06/2022
Horário: 9h
Esta banca ocorrerá de forma remota. Interessados em assistir a defesa poderão acessar a sala virtual através do link: https://meet.google.com/syz-qebq-pjy

Banca Examinadora:
– Prof. Dr. Luigi Carro (UFRGS)
– Prof. Dr. Ricardo dos Santos Ferreira (UFV)
– Prof. Dr. Arthur Francisco Lorenzon (UNIPAMPA)

Presidente da Banca: Prof. Dr. Gabriel Luca Nazar

Abstract: Technology scaling has been successfully improving the performance of current microprocessors mostly due to the reduced node size that enables increased transistor integration, which also allows for the design and widespread adoption of high-performance and highly heterogeneous systems. However, despite the slowdown of Moore’s Law, the high transistor integration is accompanied by difficult technological challenges and tradeoffs that must be addressed. In special, smaller technology nodes impose increased reliability, power density and process variability issues that penalize performance and energy efficiency if not properly addressed. Overcoming such challenges is specially difficult for devices operating at edge due to the limited power/thermal budgets and battery dependency. In this thesis, then, we propose a holistic methodology to improve non-functional requirements (such as performance, energy and area efficiency and reliability) for heterogeneous Multiprocessor System on a Chip (MPSoC) targeting edge-based applications subject to power, reliability and process variability constraints. First, we leverage application and microarchitectural heterogeneity of cores, and propose a low-cost learning method for application-to-core mappings that provide near-to-optimal MPSoC Mean Workload to Failure (MWTF). With the prediction-based mappings, we achieve MWTF as close as 5.6% to the oracle in a low-overhead and transparent fashion. Secondly, we propose a design-time energy efficiency strategy by adopting Near-Threshold Voltage (NTV) for MPSoCs. Because NTV degrades frequency, we propose a special NTV allocation strategy based on dynamic programming, in which only an optimal subset of the cores are set to operate at NTV, attenuating the frequency degradation overheads. During runtime, we apply proper application mapping strategy to further recover from the frequency loss. The combination of the design and runtime solutions provides improved performance under restricted power budgets constraints, alleviating the performance and area efficiency overheads imposed by NTV. As a case study, we show that our strategy enables the adoption of a power-consuming systolic array for edge-based machine learning applications that operate under restricted power budgets at the milliwatt level. Our results show that, under restricted power budgets, performance is improved by approximately 18.9% when compared to architectures that operate at conventional voltage settings. When compared to architectures operating fully at NTV, energy efficiency and area efficiency are improved by averages of 5.3 and 6.9 times, respectively, highlighting that the NTV overheads can be significantly reduced when careful optimization is considered.

Keywords: Heterogeneous systems. application mapping. reliability. near-threshold voltage. energy efficiency