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Detalhes do Evento

O Programa de Pós-Graduação em Microeletrônica – PGMICRO, da Universidade Federal do Rio Grande do Sul, tem a satisfação de convidar a Comunidade Universitária para assistir à defesa pública de  Tese de Doutorado de o aluno LEANDRO MATEUS GIACOMINI ROCHA realizar-se

Data: 25/09/2020 às 16h00min

Local: Videoconferência-:  https://mconf.ufrgs.br/webconf/00002725

Título: “Energy-Efficient Recurrent Neural Network Hardware Architecture for Heart Rate Estimation Based on Photoplethysmography”

Orientador: Prof. Dr. Sergio Bampi

Banca examinadora:                                                          

Prof. Dr. Fernando Gehm Moraes(PUCRS)

Prof. Dr. Mateus Grellert da Silva(UFSC)

Prof.ª Dr.ª Fernanda Lima Kastensmidt (UFRGS-PGMICRO)


The increasing power density and the pervasive use of compute-intensive and power-hungry applications demand energy-efficient CMOS design. The quest for energy-efficient systems particularly concerns in wearable devices for health monitoring as they must be under non-stop operation with limited energy source available on miniaturized batteries. There is an ever-growing interest in employing neural network-based applications for data processing on edge devices. Neural networks have complex structures in their pure software or hardware implementations, or in a combination of both approaches. They require millions of data fetches and arithmetic operations that are very energy demanding, and merely reducing the data sizes to meet power constraints might not be enough due to significant impact on output error. Hence, this work proposes a framework for arithmetic circuit generation, enabling an architectural exploration to seek maximize as much as possible the energy efficiency. As a case study, this thesis also proposes a co-design approach to implement a neural network-based heart rate estimation application from photoplethysmogram signals. This approach combines binarization and quantization techniques to reduce computation requirements, making the model more suitable for hardware implementation. A custom hardware architecture is proposed for this application to achieve real-time operation with maximum energy efficiency. The stream-based architecture minimizes the system latency adopting a full pipeline implementation exploring the application requirements. This architecture was validated on both FPGA and ASIC platforms to ensure its feasibility on embedded devices.

Keywords: neural networks, VLSI design, low power CMOS, hardware accelerator, heart rate estimation, PPG.