Technical Program

To access the general Chip in Bahia program please click here

Tuesday – September 1st

08:40 - 10:20 Low Power Design Essentials
Jan Rabaey, University of California at Berkeley - UCB, EUA
Room: Fernando Pessoa 2
10:40 - 10:20 Ultra-Low-Voltage (ULV) IC Design: Designing for VDD below kT/q
Márcio Cherem Schneider, Universidade Federal de Santa Catarina - UFSC, Brazil
Room: Fernando Pessoa 2
13:40 - 15:20 Impact of Low Frequency Noise on the Reliability and Variability of Nano CMOS devices
Jalal Jomaah, Institut National Polytechnique de Grenoble - INPG, France; Lebanese University
Room: Fernando Pessoa 2
3D ICs - Moving from Silicon to Heterogeneous Technologies
Maciej Ogorzalek, Jagiellonian University, Krakow, Poland
Room: Fernando Pessoa 3
15:40 - 17:20 Cyber - Physical Systems: Reality, Dreams, and Fantasy
Magdy A. Bayoumi, University of Louisiana at Lafayette, EUA
Room: Fernando Pessoa 2
Low Loss, High Isolation, Linear RF Switch Design in SOI
Peter H. Popplewell, Skyworks Solutions, Canada
Room: Fernando Pessoa 3
Room: Fernando Pessoa 1 and Fernando Pessoa 2
Hour: 18:00 to 18:20
Room: Foyer S2 & Praça Luiz de Camões
Hour: 18:40 - 20:00

Wednesday – September 2nd

08:00 - 09:40 Lessons from Brain Connectivity for Future Interconnect in ICs
Jan Rabaey, University of California at Berkeley - UCB, EUA
Room: Fernando Pessoa 1, 2, 3
Invited Talk
13:20 - 14:00 Frame Free Vision
Teresa Serrano-Gotarredona, IMSECNM-CSIC, Sevilla; University of Sevilla, Spain
Room: Fernando Pessoa 3
Session 1: Compensation at Architectural or Application Level
Room: Fernando Pessoa 3
Gilles Jacquemod - Polytechnique de Nice - France
14:00 - 14:20 An Application-Specific NBTI Ageing Analysis Method
Haider Abbas, Mark Zwolinski and Basel Halak, (University of Southampton, UK)
14:20 - 14:40 Delay Variation Compensation through Error Correction using Razor
Adelson N. Chua, Rico Jossel M. Maestro, Mark Earvin V. Alba, Wes Vernon V. Lofamia, Bernard Raymond D. Pelayo, Ken Bryan F. Fabay, John Cris F. Jardin, Kervin John C. Jocson, Joy Alinda R. Madamba, John Richard E. Hizon, and Louis P. Alarcon, (University of the Philippines Diliman, Philippines)
14:40 - 15:00 2.64 pJ Reference-Free Power Supply Monitor with a Wide Temperature Range
Hernán Cerqueira, Pablo Ituero and Marisa Lopez-Vallej, (Universidad Politecnica de Madrid, Spain)
15:00 - 15:20 Exploration of Noise Robustness and Sensitivity of Bulk Current Sensors for Soft Error Detection
João Guilherme Mourão Melo1, Frank Sill Torres1 and Rodrigo Possamai Bastos2, (Universidade Federal de Minas Gerais1, Brazil and Université de Grenoble-TIMA2, France)

Thursday – September 3rd

08:00 - 09:40 Majority-based Synthesis for Digital Nano-technologies
Giovanni de Micheli, EPFL, Switzerland
Room: Fernando Pessoa 1, 2, 3
Invited Talk
13:20 - 14:00 System-Level Design of Heterogeneous System-on-Chip Architectures
Luca Carloni, Columbia University, EUA
Room: Fernando Pessoa 3
Session 2: Simulation and Characterization of Devices and Processing Variations
Room: Fernando Pessoa 3
Chair: Nadine Azemard - LIRMM - France
15:40 - 16:00 Study And Reduction of Variability in 28nm FDSOI Technology
Gilles Jacquemod1, Zhaopeng Wei1, Jad Modad1, Emeric de Foucauld2, Frederic Hameau2, Yves Leduc1 and Philippe Lorenzini1, (Université Nice Sophia Antipolis1, France and CEA-LETI2, France)
16:00 - 16:20 Energy Study for 28nm FDSOI Technology
Rida Kheirallah1, Nadine Azemard1 and Gilles Ducharme2, (LIRMM1, France and Université Montpellier2, France)
16:20 - 16:40 Within-Die and Die-to-Die Variability on 65nm CMOS : Oscillators Experimental Results
Juan Pablo Martinez Brito1,2, Marcelo Lubaszewski1,2, and Sergio Bampi1(UFRGS1, Brazil and CEITEC S.A2, Brazil)
16:40 - 17:00 MOSFET Stacked-Pair Test Structure for Mismatch evaluation by estimating the on-resistance ratio
Juan Pablo Martinez Brito1,2, Marcelo Lubaszewski1,2, and Sergio Bampi1(UFRGS1, Brazil and CEITEC S.A2, Brazil)
17:00 - 17:20 Global statistical methodology for the analysis of equipment parameter effects on TSV formation
Frederic Roger1, Lado Filipovic2, Anderson Singulani1, Sara Carniello1 and Siegfried Selberherr2, (ams AG1, Austria and TU Wien2, Austria)

Friday – September 4th

08:00 - 09:40 A Path towards Average-Case Silicon via Asynchronous Resilient Bundled-Data Design
Peter Beerel, University of Southern California (USC) in Los Angeles, EUA
Room: Fernando Pessoa 1, 2, 3
Invited Talk
13:20 - 14:00 Rethinking "Things" Design - The Missing Technology Link in the Internet of Things (IoT)
Massimo Alioto , National Univ. of Singapore
Room: Fernando Pessoa 3
Session 3: Noise and Variability Modeling in CMOS Circuits
Room: Fernando Pessoa 3
Chair: Mark Zwolinski - Univ. of Southampton - GBR
14:00 - 14:20 Is intrinsic noise a limiting factor for subthreshold digital logic in nanoscale CMOS?
Francisco Veirano1, Fernando Silveira1 and Lirida Naviner2, (Universidad de la Republica1, Uruguay and TELECOM ParisTech2, France)
14:20 - 14:40 A Noise Suppressing Filter Design for Reducing Deconvolution Error of Both-Directions Downward Sloped Asymmeric RTN Long-Tail Distributions
Hiroyuki Yamauchi1 and Worawit Somha2, (Fukuoka Institute of Technology1, Japan and King Mongkut’s Institute of Technology Ladkrabang2, Thailand)
14:40 - 15:00 On Vth-Variation and Noise Margin Modeling
Azam Beg, (United Arab Emirates University, UAE)
15:00 - 15:20 On Schmitt Trigger Digital Gates
Mihai Tache and Valeriu Beiu, (United Arab Emirates University, UAE)


Instituto de Informática - Universidade Federal do Rio Grande do Sul
Av. Bento Gonçalves, 9500 - Campus do Vale. Bloco IV
91501-970- Porto Alegre-Brazil