Resource Positioning and Sharing in Dynamically Reconfigurable FPGA-Based Networks
GUERRA, VICTOR SBERSE, Nazar, Gabriel Luca
IEEE NETWORK (2026) Vol: EA
A variation-aware methodology for improved processor designs for the edge computing domain
TONETTO, RAFAEL B., NAZAR, GABRIEL L., BECK, ANTONIO CARLOS S.
DESIGN AUTOMATION FOR EMBEDDED SYSTEMS (2025) Vol: 29 Issue: 1
Constraint-Aware Multi-Technique Approximate High-Level Synthesis for FPGAs
LEIPNITZ, MARCOS T., NAZAR, GABRIEL L.
ACM Transactions on Reconfigurable Technology and Systems (2023) Vol: 16 Issue: 4
Modular VNF Components Acceleration With FPGA Overlays
BACHINI LOPES, FILIPE, SCHAEFFER-FILHO, ALBERTO E., Nazar, Gabriel Luca
IEEE Transactions on Network and Service Management (2023) Vol: 20 Issue: 1
PReCEP: Automatic insertion of Partial Redundancy based on Critical Error Probability
NAZAR, GABRIEL L., KOPPER, PEDRO H.C., LEIPNITZ, MARCOS T., JUURLINK, BEN
MICROELECTRONICS RELIABILITY (2021) Vol: 126
SoMMA: A software-managed memory architecture for multi-issue processors
JOST, TIAGO TREVISAN, Nazar, Gabriel Luca, Carro, Luigi
MICROPROCESSORS AND MICROSYSTEMS (2020) Vol: 77
A Survey on FPGA Support for the Feasible Execution of Virtualized Network Functions
NIEMIEC, GABRIEL S., BATISTA, LUIS M. S., SCHAEFFER-FILHO, ALBERTO E., NAZAR, GABRIEL L.
IEEE Communications Surveys and Tutorials (2020) Vol: 22 Issue: 1
High-Level Synthesis of Approximate Designs under Real-Time Constraints
LEIPNITZ, MARCOS T., NAZAR, GABRIEL L.
ACM Transactions on Embedded Computing Systems (2019) Vol: 18 Issue: 5s
Exploring the limitations of dataflow SIHFT techniques in out-of-order superscalar processors
CARDOSO, D.M., TONETTO, R., BRANDALERO, M., NAZAR, G., BECK, A.C., AZAMBUJA, J.R.
MICROELECTRONICS RELIABILITY (2019) Vol: -
Repair of FPGA-Based Real-Time Systems With Variable Slacks
PEREIRA-SANTOS, LEONARDO, Nazar, Gabriel Luca, Carro, Luigi
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS (2018) Vol: 23 Issue: 2
Fault Tolerance Mechanisms for FPGA-Based Regular Expression Matching
LEIPNITZ, MARCOS T., NAZAR, GABRIEL L.
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS (2018) Vol: 34 Issue: 4
Exploring redundancy granularities to repair real-time FPGA-based systems
PEREIRA-SANTOS, LEONARDO, NAZAR, GABRIEL L., Carro, Luigi
MICROPROCESSORS AND MICROSYSTEMS (2017) Vol: 51
Beyond Cross-Section
SANTINI, T., RECH, P., NAZAR, G. L., WAGNER, F. R.
ACM Transactions on Embedded Computing Systems (2016) Vol: 15 Issue: 1
Live-Out Register Fencing
FERREIRA, RONALDO R., NAZAR, GABRIEL L., ROLT, JEAN DA, MOREIRA, ÁLVARO F., Carro, Luigi
ACM Transactions on Embedded Computing Systems (2016) Vol: 15 Issue: 3
Improving FPGA repair under real-time constraints
NAZAR, GABRIEL L.
Microelectronics and Reliability (2015) Vol: 55 Issue: 7
GPUs Reliability Dependence on Degree of Parallelism
RECH, P., NAZAR, G. L., FROST, C., CARRO, L.
IEEE Transactions on Nuclear Science (2014) Vol: 61 Issue: 4
Adaptive Parallelism Exploitation under Physical and Real-Time Constraints for Resilient Systems
ITTURIET, FÁBIO, NAZAR, GABRIEL, FERREIRA, RONALDO, MOREIRA, ÁLVARO, Carro, Luigi
ACM Transactions on Reconfigurable Technology and Systems (2014) Vol: 7 Issue: 3
Fine-Grained Fast Field-Programmable Gate Array Scrubbing
Nazar, Gabriel Luca, SANTOS, LEONARDO PEREIRA, Carro, Luigi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Print) (2014) Vol: 23 Issue: 5
Evaluating Neutron Induced SEE in SRAM-Based FPGA Protected by Hardware- and Software-Based Fault Tolerant Techniques
AZAMBUJA, JOSE RODRIGO, NAZAR, GABRIEL, RECH, PAOLO, Carro, Luigi, KASTENSMIDT, FERNANDA LIMA, FAIRBANKS, THOMAS, QUINN, HEATHER
IEEE Transactions on Nuclear Science (2013) Vol: 60 Issue: 6
Radiation and Fault Injection Testing of a Fine-Grained Error Detection Technique for FPGAs
NAZAR, GABRIEL L., RECH, PAOLO, FROST, CHRISTOPHER, Carro, Luigi
IEEE Transactions on Nuclear Science (2013) Vol: 60 Issue: 4
ASIC Design and Implementation of Low Latency and High Throughput FFT and iFFT
AMARAL, L. P., PEREIRA, P. T. L., GRELLERT, M., NAZAR, G. L.
IEEE Latin American Symposium on Circuits and Systems (LASCAS) (2026)
FPGAs for Network Function Virtualization: Challenges in Placement and Partitioning
GUERRA, V. S., NAZAR, G. L.
Symposium on Integrated Circuits and Systems Design (SBCCI) (2024)
A Partition-Aware VNF Placement Methodology for FPGA-Equipped NFVIs
GUERRA, V. S., NAZAR, G. L.
Simpósio Brasileiro de Redes de Computadores e Sistemas Distribuídos (SBRC) (2024)
GRASP-based High-Level Synthesis Design Space Exploration for FPGAs
SCHUSTER, N. P., NAZAR, G. L.
Brazilian Symposium on Computing Systems Engineering (SBESC) (2023)
SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing
TONETTO, R., BECK, A. C. S., NAZAR, G. L.
Euromicro Conference on Digital System Design (DSD) (2022)
VNFAccel: An FPGA-based Platform for Modular VNF Components Acceleration
LOPES, F. B., NAZAR, G. L., SCHAEFFER-FILHO, A. E.
IFIP/IEEE International Symposium on Integrated Network Management (IM) (2021)
Lightweight Dual Modular Redundancy through Approximate Computing
NAZAR, G. L., KOPPER, PEDRO H.C., LEIPNITZ, M. T., JUURLINK, BEN
Brazilian Symposium on Computing System Engineering (SBESC) (2021)
Evaluation of high-level languages for general FPGA acceleration
SAAVEDRA, A., NAZAR, G. L., STAWINOGA, N., JUURLINK, BEN
International Summer School on Advanced Computer Architecture and Compilation for High-performance Embedded Systems (2021)
High-level synthesis of throughput-optimized and energy-efficient approximate designs
LEIPNITZ, MARCOS T., NAZAR, G. L.
ACM International Conference on Computing Frontiers (2020)
Enhancing Real-Time Motion Estimation Through Approximate High-Level Synthesis
LEIPNITZ, M. T., PERLEBERG, M. R., PORTO, M., NAZAR, G. L.
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2020)
ACQuA: A Parallel Accelerator Architecture for Pure Functional Programs
COELHO, R. A., TANUS, F., MOREIRA, A. F., NAZAR, G. L.
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2020)
A Machine Learning Approach for Reliability-Aware Application Mapping for Heterogeneous Multicores
TONETTO, R. B., ROCHA, H. M. G. A., NAZAR, G. L., BECK, A. C. S.
Design Automation Conference (2020)
Low-Power and Memory-Aware Approximate Hardware Architecture for Fractional Motion Estimation Interpolation on HEVC
PENNY, W., CORREA, G., AGOSTINI, L., PALOMINO, D., PORTO, M., NAZAR, G. L., ZATT, B.
IEEE International Symposium on Circuits and Systems (2020)
A Reliability-Oriented Machine Learning Strategy for Heterogeneous Multicore Application Mapping
TONETTO, R. B., ROCHA, H. M. G. A., ZATT, B., BECK, A. C. S., NAZAR, G. L.
IEEE International Symposium on Circuits and Systems (2020)
Firefly: An Open-source Rocket-based Intermittent Framework
ROCHA, H. M. G. A., BECK, A. C. S., KOROL, G., JORDAN, M., KRAUSE, A., SILVEIRA, R., VIEIRA, C., NAVAUX, P. O. A., NAZAR, G. L., CARRO, L.
Symposium on Integrated Circuits and Systems Design (SBCCI) (2020)
Throughput-Oriented Spatio-Temporal Optimization in Approximate High-Level Synthesis
LEIPNITZ, M. T., NAZAR, G. L.
International Conference on Computer Design (2020)
Cost-effective Resilient FPGA-based LDPC Decoder Architecture
SOUZA, E. N., NAZAR, G. L.
IEEE International On-Line Testing Symposium (2019)
High-Level Synthesis of Resource-oriented Approximate Designs for FPGAs
LEIPNITZ, M. T., NAZAR, G. L.
Design Automation Conference (2019)
A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors
TONETTO, R. B., CARDOSO, D. M., BRANDALERO, M., AGOSTINI, L. V., NAZAR, G. L., AZAMBUJA, J. R., BECK, A. C. S.
International Conference on Very Large Scale Integration (2019)
Exploring the Limitations of Dataflow SIHFT Techniques in Out-of-Order Superscalar Processors
CARDOSO, D. M., TONETTO, R. B., BRANDALERO, M., NAZAR, G. L., BECK, A. C. S., AZAMBUJA, J. R.
European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF) (2019)
Improving Software-Based Techniques for Soft Error Mitigation in OoO Superscalar Processors
CARDOSO, D. M., TONETTO, R. B., BRANDALERO, M., AGOSTINI, L. V., NAZAR, G. L., BECK, A. C. S.
IEEE International Conference on Electronics, Circuits and Systems (2019)
Energy-efficiency exploration of memory hierarchy using nvms for hevc motion estimation
PENNY, W., GOEBEL, J., CORREA, D., MARTINS, A., NAZAR, G. L., AGOSTINI, L., PALOMINO, D., PORTO, M., ZATT, B.
IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2019)
Precise evaluation of the fault sensitivity of OoO superscalar processors
TONETTO, RAFAEL BILLIG, NAZAR, GABRIEL L., Beck, Antonio Carlos Schneider
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) (2018)
An Energy-Efficient Memory Hierarchy for Multi-Issue Processors
JOST, T., NAZAR, G. L., CARRO, L.
Design, Automation and Test in Europe Conference and Exhibition (DATE) (2017)
A fault injection platform for FPGA-based communication systems
LEIPNITZ, MARCOS T., GEFERSON, L. H., NAZAR, GABRIEL L.
2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS) (2016)
Low Cost Dynamic Scrubbing for Real-Time Systems
SANTOS, L. P., NAZAR, G. L., CARRO, L.
International Symposium on Applied Reconfigurable Computing (ARC) (2016)
Searching with a Corrupted Heuristic
LELIS, L. H. S., VALENZANO, R., NAZAR, G. L., STERN, R.
SoCS - International Symposium on Combinatorial Search (2016)
Low Cost Resilient Regular Expression Matching on FPGAs
LEIPNITZ, M. T., SOUZA, E. N., NAZAR, G. L.
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) (2016)
Improving Performance in VLIW Soft-core Processors through Software-controlled ScratchPads
JOST, T., NAZAR, G. L., CARRO, L.
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (2016)
Scalable memory architecture for soft-core processors
JOST, TIAGO T., NAZAR, GABRIEL L., Carro, Luigi
2016 IEEE 34th International Conference on Computer Design (ICCD) (2016)
Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture
FERREIRA, RONALDO R., SANCHEZ, ERNESTO, ROLT, JEAN DA, NAZAR, GABRIE L., MOREIRA, ALVARO F., Carro, Luigi, REORDA, MATTEO SONZA
2015 16th LatinAmerican Test Symposium (LATS) (2015)
Reducing Embedded Software Radiation-Induced Failures Through Cache Memories
SANTINI, T., RECH, P., NAZAR, G. L., CARRO, L., WAGNER, F. R.
IEEE European Test Symposium (ETS) (2014)
A Checkpoint-Deterministic Architecture for Reliable and Low-Power Embedded Computing
FERREIRA, R. R., DA ROLT, J., NAZAR, G. L., MOREIRA, A. F., CARRO, L.
Workshop on Highly-Reliable Power-Efficient Embedded Designs (HARSH) (2014)
Lightweight DMR for SEE Hardening in Low Power Embedded Systems
FERREIRA, R. R., DA ROLT, J., NAZAR, G. L., MOREIRA, A. F., CARRO, L.
Nuclear and Spade Radiation Effects Conference (NSREC) (2014)
Adaptive Low-Power Architecture for High-Performance and Reliable Embedded Computing
FERREIRA, R. R., DA ROLT, J., NAZAR, G. L., MOREIRA, A. F., CARRO, L.
Annual IEEE/IFIP International Conference on Dependable Systems and Networks (2014)
Reliable Execution of Statechart-Generated Correct Embedded Software under Soft Errors
FERREIRA, R. R., KLOTZ, T., VORTLER, T., DA ROLT, J., NAZAR, G. L., MOREIRA, A. F., CARRO, L., EINWICH, K.
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (2014)
Measuring the impact of voltage scaling for soft errors in SRAM-based FPGAs from a designer perspective
TONFAT, J., BEZERRA, E., FROST, C., AZAMBUJA, J. R., NAZAR, G. L., RECH, P., KASTENSMIDT, F. L., CARRO, L., REIS, R., BENFICA, J., VARGAS, F.
Annual International Mixed-Signals, Sensors and Systems Test Workshop (2014)
Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity
BRUNI, G., RECH, P., TAMBARA, L., NAZAR, G. L., KASTENSMIDT, F. L., REIS, R., PACCAGNELL, A.
International Conference on Very Large Scale Integration (2014)
Investigating Reliability-Critical Components of VLIW Processors
TABORDA, T. B., NAZAR, G. L., CARRO, L.
5th Workshop on Design for Reliability (DFR 2013) (2013)
A Fully Dynamic Reconfigurable NoC-based MPSoC: The Advantages of Total Reconfiguration
SANTOS, P. C., NAZAR, G. L., ANJAM, F., WONG, S., MATOS, D., CARRO, L.
Workshop on Reconfigurable Computing (WRC) (2013)
Evaluating the Weighted Fault Sensitivity of the Components of a VLIW Architecture
TABORDA, T. B., NAZAR, G. L., CARRO, L.
Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms (DITAM) (2013)
A Fully Dynamic Reconfigurable NoC-based MPSoC: The Advantages of a Multi-Level Reconfiguration
SANTOS, P. C., NAZAR, G. L., ANJAM, F., WONG, S., MATOS, D., CARRO, L.
Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms (DITAM) (2013)
Accelerated FPGA repair through shifted scrubbing
NAZAR, GABRIEL L., SANTOS, LEONARDO P., Carro, Luigi
2013 23rd International Conference on Field Programmable Logic and Applications (FPL) (2013)
Dynamically Shifted Scrubbing for Fast FPGA Repair
SANTOS, L. P., NAZAR, G. L., CARRO, L.
2nd Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) (2013)
Analyzing the influence of voltage scaling for soft errors in SRAM-based FPGAs
TONFAT, JORGE, VARGAS, FABIAN, BEZERRA, EDUARDO, AZAMBUJA, JOSE RODRIGO, NAZAR, GABRIEL, RECH, PAOLO, FROST, CHRISTOPHER, KASTENSMIDT, FERNANDA LIMA, Carro, Luigi, REIS, RICARDO, BENFICA, JULIANO
2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS) (2013)
Evaluating the effectiveness of a diversity TMR scheme under neutrons
TAMBARA, LUCAS A., KASTENSMIDT, FERNANDA L., AZAMBUJA, JOSE RODRIGO, CHIELLE, EDUARDO, ALMEIDA, FELIPE, NAZAR, GABRIEL, RECH, PAOLO, FROST, CHRISTOPHER, LUBASZEWSKI, MARCELO S.
2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS) (2013)
Scrubbing unit repositioning for fast error repair in FPGAs
NAZAR, GABRIEL L., SANTOS, LEONARDO P., Carro, Luigi
2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) (2013)
Fast error detection through efficient use of hardwired resources in FPGAs
NAZAR, G. L., CARRO, L.
2012 17th IEEE European Test Symposium (ETS) (2012)
Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs
NAZAR, G. L., CARRO, L.
IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) (2012)
Simultaneous Reconfiguration of Issue-width and Instruction Cache for a VLIW Processor
ANJAM, F., WONG, S., CARRO, L., NAZAR, G. L., RUTZIG, M. B.
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (2012)
Adaptive Parallelism Exploitation under Physical and Real-Time Constraints for Resilient Systems
ITTURRIET, F. P., NAZAR, G. L., FERREIRA, R. R., MOREIRA, A. F., CARRO, L.
International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) (2012)
Resilient Adaptive Algebraic Architecture for Parallel Detection and Correction of Soft Errors
ITTURRIET, F. P., FERREIRA, R. R., GIRÃO, G., NAZAR, G. L., MOREIRA, A. F., CARRO, L.
15th Euromicro Conference on Digital System Design (2012)
Experimental Evaluation of an Efficient Error Detection Technique for FPGAs
NAZAR, G. L., RECH, P., FROST, C., CARRO, L.
European Conference on Radiation and Its Effects on Components and Systems (RADECS) (2012)
Adapting Communication for Adaptable Processors: A Multi-Axis Reconfiguration Approach
SANTOS, P. C., NAZAR, G. L., ANJAM, F., WONG, S., CARRO, L.
2012 International Conference on ReConFigurable Computing and FPGAs (ReConFig) (2012)
Fast single-FPGA fault injection platform
NAZAR, G. L., CARRO, L.
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) (2012)
Energy Efficient Pseudo-Cache Architecture Through Fine-Grained Reconfigurability
NAZAR, G. L., CARRO, L.
International Symposium on Circuits and Systems (ISCAS) (2011)
An Area Effective Parity-based Fault Detection Technique for FPGAs
NAZAR, G. L., CARRO, L.
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (2011)
Implementation comparisons of the QR decomposition for MIMO detection
NAZAR, G. L., GIMMLER, C., WEHN, N.
Symposium on Integrated Circuits and Systems Designs (SBCCI) (2010)
Implementação de uma arquitetura reconfigurável em um FPGA
NAZAR, G. L., BECK, A. C. S.
Salão de Iniciação Científica (2008)
