Thierry Taris (IMS - University of Bordeaux, France)
RF CMOS Design with the Inversion Coefficient

Abstract:
The emergence of the Internet of Things (IoT) posesstringent requirements on the energy consumption and has hence highlyconstrained power and area budgets, while circumventing the challengesposed by modern device technologies, makes analog and RF circuit designever more challenging. Some guidance would therefore be invaluable forthe designer to navigate the multi-variable design space. This talkfirst introduces the concept of inversion coefficient IC as an essentialdesign parameter for analog RF design. The IC is exploited to implementand optimize RF building blocks such as Low Noise Amplifiers (LNA) andOscillators in 28nm CMOS FD SOI, 65nm and 130nm CMOS Bulk Technologies.The combination of some high frequency functions is also revisitedto further reduce the power consumption of the RF front-end.

Short Bio:
Thierry TARIS received his PhD degree in 2003 from the University ofBordeaux and is now Professor at Bordeaux Institut of Technology(Bordeaux-INP). His research focuses on the design of RF front end onadvanced CMOS/BiCMOS technologies. Dr. Taris is responsible for thecircuit design activities at the STMicro-IMS joined lab. He haspublished more than 80 papers in international journals andconferences, and is co-inventor of 6 patents. He is an invited professorof the University of British Columbia (UBC), Vancouver, Canada, andEcole Polytechnic Federal de Lausanne (EPFL), Lausanne, Switzerland.

Gyuszi Suto (Intel, USA)
Talk 1:The Challenges and Beauty of Cell-level Physical Design

Abstract:
This talk will present the evolution of physical design constraints - spanning the last two decades – covering the shapes, directions, gridding, design rules and discretization of the layout building blocks used for the devices and standard cells for VLSI design. It will introduce the audience to multi-object constraints, to fabrics and restrictive design space and the natural transition from traditional (sequential) VLSI CAD algorithms to more formal (simultaneous, SAT-based) solvers.

Short Bio:
Gyuszi Suto is a Principal Engineer at Intel corporation where he spent the past 23 years in Physical Design CAD covering design rule modeling, channel routing, global routing, detail routing, placement, fill, yield and automatic cell synthesis. Main author of four Intel patents related to Physical Design. Was attending member of the ANSI/ISO C++ committee during the first standardization effort that led to the C++98 standard. Taught C++ programming to Intel programmers for 23 years. Main organizer of yearly Intel internal programming contest and programmers’ day since 2008. Main architect and co-author of boost::Polygon open-source C++ library. Prior to Intel Gyuszi spent three years at an unsuccessful startup company Privac Inc. where he worked on the board-level CAD and compiler of a low-cost VLIW supercomputer. Gyuszi graduated from the Technical University of Cluj-Napoca Romania with a degree in Computer Science and Engineering. Prior to his move to the United States in 1990 Gyuszi worked three years at an electric motor company in Romania. Gyuszi is passionate about programming, puzzles, math and teaching.

Frank Sill Torres (UFMG, Brazil)
QUANTUM-DOT CELLULAR AUTOMATA (QCA) - A new way of nano-computation

Abstract:
Quantum-dot Cellular Automata (QCA) is one of the most interesting among the emerging technologies for design of integrated designs. Over the last few decades since its inception at the University of Notre Dame, QCA has dramatically evolved in a dynamic and exciting field of investigation with contributors from all over the world. QCA is a challenging nanotechnology that due to its unique structural and operational features represents a revolutionary departure from current practice. QCA relies on principles that are fundamentally different from CMOS and therefore, it may offer unprecedented advantages to solve those challenges that are expected to occur at the end of the technology roadmap. This talk will give an introduction into the technological concepts of this new nanotechnology, discuss the design of digital circuits based on QCA, introduce a design and simulation tool, explore the integration in existing design flows, and discuss robustness challenges.

Short Bio:
Frank Sill Torres received his diploma (2002) and Ph.D. degree (2007) in Electrical Engineering from the University of Rostock, Germany. From 2007 to 2009 he was as Post-Doc at the Federal University of Minas Gerais, Brazil. Since 2010, he is an Adjunct Professor at the Department of Electronic Engineering, Federal University of Minas Gerais (UFMG), Brazil, and permanent member of the Post-graduation programs in Electrical Engineering of the UFMG and the Federal University of Manaus (UFAM). His main research interests involve Emerging nanotechnologies, Design for reliability, Low-power VLSI design, and Electronic Design Automation. Frank Sill Torres is the coordinator of the “ASIC Reliability Group (OptMA/ART)” and sub-coordinator of the Laboratory for Optronics and Microtechnologies (OptMAlab) at the UFMG. Frank is a member of several conference committees, an Associate Researcher of the Brazilian National Research Council and author and co-author of more than 60 publications in scientific journals and congresses.

Posters Session and Coffee Break

- Exploring Circuit Signal Probabilities to Static Leakage, Aging and Reliability Evaluation. Augusto A. S. Berndt and Paulo F. Butzen.

- An Introduction To Integrated Circuits Layouts Design Using Educational Tools. Renner R. Brandão, Tarlei Almeida and Rafael V. T. Nobrega.

- Exploring Alternative Designs of Majority Voters. Ingrid Oliveira, Rafael Schivittz, Eduardo Liebl, Cristina Meinhardt and Paulo Butzen.

- Matlab Script of a BJT Radiation Model for Bandgap Reference Circuit Simulation. Aldair Wontroba, João Baptista Martins and André Luiz Aita.

- Automatic Design of an OTA Miller in 0.13μm Technology Considering Yield Optimization. Robson Domanski, Luiz Da Silva, Alessandro Girardi and Paulo César Comassetto de Aguirre.

- EEC: ELECTRONIC ELDERLY CARE - A remote monitoring system for elder care. Laura Ramos, Lucas Lanzarini, Thanise Dutra and Calebe Conceicao.

- HARDWARE DESIGN FOR THE HEVC IDCT TARGETING REAL-TIME APPLICATIONS. Jones Goebel, Ruhan Conceição, Bruno Zatt, Luciano Agostini and Marcelo Porto.

- Comparison of Voltage Scaling for XOR logic gates between planar MOSFET and FinFET technology at 16nm. Leonardo H. Brendler, Alexandra L. Zimpeck, Ygor Aguiar and Ricardo Reis.

- Low-Power and High-Throughput Hardware for VP9-10 Sub-Sample Interpolator. Jones Goebel, Guilherme Paim, Vladimir Afonso, Luciano Agostini, Bruno Zatt, Marcelo Porto, Wagner Penny and Altamiro Susin.

- Global Positioning Cells with Strange Attractors. A New Approach. Elias de Almeida Ramos, Guilherme Bontorin and Ricardo Reis.

- FPGA Based Implementation of a Real Time Control on Robots. Valquiria Huttner, Cristiano Steffens and Silvia Botelho.

- Evaluation of Performance and Power Analysis for 1-bit Full Adders Topologies in FinFET and Planar MOSFET. Pablo M. Da Silva, Alexandra L. Zimpeck, Ygor Aguiar and Ricardo Reis.

- Voltage Scaling behavior. Clayton Farias.

- Automatic Search for Audio Pattern in Radio and TV Transmissions. Natália Winter Rovaris, Arthur Ferrari Sofiatti, Tiago Roberto Balen, Igor Gustavo Hoelscher and Altamiro Amadeu Susin.

- Brazilian Digital TV System Project. Ana Luiza Pereira Brod, Bruna Carvalho, Bruno Forlin, Frederico Liz, Paulo Kipper, Pedro Portugal, Cezar Reinbrecht, Bruno Policarpo and Altamiro Susin.

- Brazilian Digital TV System Software Architecture. Pedro Portugal, Cezar Rodolfo Wedig Reinbrecht, Ana Luiza Brod, Bruno Forlin, Frederico Liz, Bruno Policarpo and Altamiro Susin.

- Brazilian Digital TV System Hardware Architecture. Paulo Kipper, Cezar Rodolfo Wedig Reinbrecht, Altamiro Susin, Bruna Carvalho and Marcelo Negreiros.

Mustafa Ozdal (Bilkent University, Turkey)
Hardware Accelerators for Graph Analytics

Abstract:
Energy consumption of data centers have increased significantly in the last decade. Heterogeneous architectures with hardware accelerators can significantly improve the energy efficiency of computation. In this talk, we focus on graph analytics applications and discuss the architectural features required to execute such applications efficiently.

Short Bio:
Mustafa Özdal is a professor at Bilkent University, Turkey. He received both his B.S. and M.S degrees from Bilkent University in 1999 and 2001, respectively. He received his PhD degree in Computer Science from Univ. of Illinois at Urbana-Champaign in 2005. He was a research scientist in the Strategic CAD Labs of Intel, Oregon until September 2015. He has served in the executive and the technical program committees of several conferences. He is a recipient of the IEEE/ACM William J. McCalla ICCAD Best Paper Award (2011), ACM SIGDA Technical Leadership Award (2012), and the European Commission MSCA Individual Fellowship (2016). His current research interests include algorithms for big data problems, high performance computing, parallel and heterogeneous computing, computer-aided design algorithms, and hardware/FPGA accelerators for big data applications.

Gyuszi Suto (Intel, USA)
Talk 2: How To Breed Programmers for VLSI Physical Design CAD

Abstract:
This talk will cover a personal account on how to find, interview, train, challenge and motivate the best programmers for the near-impossible task of solving NP-hard problems inherent to VLSI Physical Design. It will introduce the audience to various programming habits, eight years of programming contests, puzzles, team-dynamics and communication styles that helped build highly functional development teams.

Short Bio:
Gyuszi Suto is a Principal Engineer at Intel corporation where he spent the past 23 years in Physical Design CAD covering design rule modeling, channel routing, global routing, detail routing, placement, fill, yield and automatic cell synthesis. Main author of four Intel patents related to Physical Design. Was attending member of the ANSI/ISO C++ committee during the first standardization effort that led to the C++98 standard. Taught C++ programming to Intel programmers for 23 years. Main organizer of yearly Intel internal programming contest and programmers’ day since 2008. Main architect and co-author of boost::Polygon open-source C++ library. Prior to Intel Gyuszi spent three years at an unsuccessful startup company Privac Inc. where he worked on the board-level CAD and compiler of a low-cost VLIW supercomputer. Gyuszi graduated from the Technical University of Cluj-Napoca Romania with a degree in Computer Science and Engineering. Prior to his move to the United States in 1990 Gyuszi worked three years at an electric motor company in Romania. Gyuszi is passionate about programming, puzzles, math and teaching.

Julius Georgiou (DL IEEE CASS) (University of Cyprus)
Microelectronic Systems for Improved Quality of Life

Abstract:
Microelectronic revolutions come in waves that are driven by necessity. Currently, the aging population is creating a need for various kinds of electronic systems to improve their quality of life. These include the restoration of lost functionality via electronic implants, better health screening technology and non-invasive monitoring in the home environment. In this talk I will present work that has been done towards addressing these needs, whether it be through the development of new required building blocks or through the development of more complex systems that combine custom built hardware and software. In particular the talk covers work done towards developing a vestibular implant for balance restoration, a single chip low-power imager for a bionic eye, a cancer screening capsule for detecting early-stage carcinomas in the small intestine and a bio-inspired acoustic scene analysis system.

Short Bio:
Prof. Julius Georgiou is a member of the IEEE Circuits and Systems Society, is the Vice-Chair of the BioCAS Technical Committee, as well as a member of the IEEE Circuits and Systems Society Analog Signal Processing Technical Committee. He served as the General Chair of the 2010 IEEE Biomedical Circuits and Systems Conference and is the Action Chair of the EU COST Action ICT-1401 on “Memristors-Devices, Models, Circuits, Systems and Applications – MemoCIS”. Prof. Georgiou has been selected as an IEEE Circuits and Systems Society Distinguished Lecturer for 2016-2017. He is also is an Associate Editor of the IEEE Transactions on Biomedical Circuits and Systems and Associate Editor of the Frontiers in Neuromorphic Engineering Journal. He is a recipient of a best paper award at the IEEE ISCAS 2011 International Symposium and at the IEEE BioDevices 2008 Conference.His research interests include Low-power analog and digital ASICs, implantable biomedical devices, bioinspired electronic systems, electronics for space, brain-computer-interfaces (BCIs), memristive devices, inertial and optical sensors and related systems.

Alfredo Arnaud Maceira (Universidad Católica del Uruguay)
Power Management in the Nano-Ampere Era.

Abstract:
Power consumption constrain is a major concern in modern electronics, and because of energy harvesting techniques, highly integrated portables,and the new battery technologies, there is a renewed academic and industrial interest in fully operative circuits with a current consumption below the uA. A very important aspect to take into account is power management at this boundary, to drain the minimum possible current from a battery at a given circuit performance. In this presentation first of all the power consumption of both analog and digital circuits, including static power, will be examined in detail. We will discuss some issues like: what is the minimum current for an analog circuit to operate?, or what is the minimum voltaje for a digital circuit? Some modern techniques to maximize battery energy harnessing will be presented, including recent advances in current reuse techniques. Then micro and nano-watt DC-DC converters will be discussed, including a survey and circuit examples of micro-power integrated charge pumps, and micro-power switching inductor converters.

Short Bio:
Dr. Alfredo Arnaud received his PhD, and MSc from UdelaR, Montevideo–Uruguay, in 2004 and 2000, respectively. Since 2004 he joined Electrical Engineering Department (DIE) at Universidad Católica del Uruguay, where he started microDIE research group. Dr.Arnaud holds two patents and as an academic he published more than 70 papers in international journals and scientific meetings, and participated in 20 funded R&D projects. He is the co-founder of two technology companies: BQN in 2004 (http://www.bqn.com.uy) dedicated to HW & SW development for RFID devices & traceability within de agribusiness industry, POS, medical instrumentation, among others, and Chipmate in 2009 (http://www.chipmateic.com) a spin-off of the microDIE aimed at the design of ASICs for medical devices and others. For the industry, Dr. Arnaud participated in design and consultancy in the field of microelectronics for implantable medical devices in five different occasions for companies in Uruguay, Brazil, Canada, and India. Dr. Arnaud also participated in the development of embedded electronics like portable POS equipment, a USB dynamic scale for medical applications, and a portable RFID reader according to ISO11784/11785 standard

Posters Session and Coffee Break

- Investigating Fault Collapsing Methods for Test Pattern Generation. Gabriel S. Porto, Paulo F. Butzen and Denis T. Franco.

- A Built-In Self-Test and Fault Detection Algorithm Implementation for NAND Flash. Guilherme Lopes and Margrit Krug.

- Evaluating the Efficiency of Software-based Fault Tolerant Techniques to Detect SEUs in GPUs. Mateus Tirone, Márcio Gonçalves and José Azambuja.

- harge Pump Phase-Locked Loop CP-PLL for Clock Generation. Raphael Souza and Agord Pinto Junior.

- Probabilistic models to improve PTM technique accuracy. Rafael Schivittz, Cristina Meinhardt and Paulo F. Butzen.

- Runtime Management of Multiprocessor System-on-Chip using FreeRTOS. Geancarlo Abich, Felipe Da Rosa, Vitor Bandeira, Luciano Ost and Ricardo Reis.

- FDSOI and Bulk CMOS SRAM Cells Resilience to Radiation Effects. Walter Calienes Bartra, Andrei Vladimirescu and Ricardo Reis

- A parallel architecture for the HEVC Quantizer without using multipliers. Luciano Braatz, Luciano Agostini, Bruno Zatt and Marcelo Porto.

- Online Remaining Lifetime Prediction for Integrated Systems. Pedro Fausto Rodrigues Leite Junior and Frank Sill Torres.

- An Implementation of an algorithm for global placement. Henrique Plácido.

- Integrating Elmore delay in the quadratic placement objective for timing optimization. Mateus Fogaça, Guilherme Flach, Jucemar Monteiro, Marcelo Johann and Ricardo Reis.

- Reducing Number of Transistors by Logic Gate Merging. Luciana Mendes Da Silva, Calebe Micael de Oliveira Conceição, Guilherme Bontorin and Ricardo Reis.

- Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation. Carlos Aguilera, Cristiano Chenet, Tiago Balen and Matheus Budelon.

- A Fully Integrated Class-AB CMOS Power Amplifier for WLAN. Gabriel Guimaraes, Hamilton Klimach and Sergio Bampi.

- Noise margins analysis of 1-bit SRAM cells. Roberto Almeida, Paulo F. Butzen and Cristina Meinhardt.

- A 0.3 V Picowatt 3-Transistor Temperature-Compensated CMOS Voltage Reference. Arthur Campos de Oliviera, David Cordova, Hamilton Duarte Klimach and Sergio Bampi.

- CMOS RF Class-E Power Amplifier with Power Control. Diogo Santana, Hamilton Klimach and Sergio Bampi.

- Wideband Inductorless Balun LNA Topologies for Sub-GHz Applications. Arthur Liraneto Torres Costa, Hamilton Klimach and Sergio Bampi.

- Symmetrical MOS Ladder DAC with Improved Linearity for Ultra-Low Voltage Applications. Israel Sperotto, Hamilton Klimach and Sergio Bampi.

- A Switched Capacitor DC – DC Converter approach for Photovoltaic Energy Harvesting. Roger Zamparette, Hamilton Klimach and Sergio Bampi.

- Clustering Analysis for Early Lithographic Hotspot Classification. Julia Puget, André Oliveira, Carolina Metzler and Ricardo Reis.

Andrea Labrudi Tavares (Cadence Brazil)
Democratization of Formal Verification with JasperGold

Abstract:
Formal verification has become an essential method for design, integration and verification of the emerging design IPs and complexsystems-on-chips. Despite the great success in proliferating formal in the industry and making it a great companion to simulation and emulation methods, its full power has not been leveraged yet to address the larger spectrum of applications by non-formal experts. To handle this challenge a major effort is still needed to boost its scalability and usability to cope with the emerging complexity of design under verification. In this talk we discuss strategies for boosting the productivity of formal verification used in JasperGold. We explain some of the automatic flows, including Hardware Security and Clock Domain Crossing, that are being developed in Brazil.

Short Bio:
Dr. Andrea Tavares is Director of R&D and Software Architect at Cadence in the Formal and Automated Verification business unit. Before joining Cadence, Andrea was a Professor at Universidade Federal de Ouro Preto, with special interest in Artificial Intelligence and Algorithms. She has almost 10 years professional experience in EDA industry and another 10 years in Telecommunication, GIS and Spatial Statistics. She received his B. Sc., M. Sc. and Ph. D. degrees in Computer Science from UFMG and her thesis was about “Cooperative Decentralized Decision Under Uncertainty and Limited Communication”.