Ebroul Izquierdo - Queen Mary - University of London (England)
Face Recognition in the Wild

Abstract:
Automated face recognition is one of the oldest and probably best understood tasks in computer vision. Due to the plethora of applications, it is also the basis for a fast evolving technology drawing attention from researchers and practitioners in several fields including forensics, biometrics, visual information retrieval, automated surveillance and internet driven social networking. Despite its maturity, face recognition algorithms fail badly when the image capturing conditions are not ideal. Furthermore, in most critical applications it requires extremely high accuracy under very adverse conditions including significant variations in image quality, scale, orientation, noise and distortions induced by other faces or objects in the same image. This makes an already difficult problem even harder. In this talk, important aspects of face recognition and few crucial applications will be presented. Starting with key open technical challenges, some important generic aspects of face recognition will be discussed. The state of the art in face recognition technology will be then outlined. The talk will subsequently refer to essential mathematical and statistical methods used to achieve highly accurate face recognition, as well as, the advantages and disadvantages of available algorithmic solutions. The usefulness of face recognition, as a tool to help forensic investigators when mining the vast amounts of data in crime solving, will be presented. Furthermore, examples of recent technological developments in two specific application scenarios will be presented. The first one relates to the recognition of people across a social networks and consumer photo collection by exploiting contextual information extracted from social semantics. The second refers to recent theoretical developments that promise to deliver a quantum leap in the accuracy of face extraction and recognition under very adverse conditions.

Short Bio:
Ebroul Izquierdo, PhD, MSc, CEng, FIET, SMIEEE, MBMVA, is Chair of Multimedia and Computer Vision and head of the Multimedia and Vision Group in the school of Electronic Engineering and Computer Science at Queen Mary, University of London. Prof. Izquierdo is a IET Chartered Engineer, a member of the Visual Signal Processing and Communications Technical Committee of the IEEE Circuits and Systems Society and member of the Multimedia Signal Processing technical committee of the IEEE. He has been associated editor of the IEEE Transactions on Circuits and Systems for Video Technology (from 2002 to 2010), the IEEE Transactions on Multimedia (from 2010 to 2015). He is member of the editorial board of the EURASIP Journal on Image and Video processing (from 2004 to date) and several other international journals in the field. Prof. Izquierdo has been member of the organizing committee of several conferences and workshops in the field of image and video processing including The IEEE International Conference on Image Processing (ICIP), The IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), The IEEE International Symposium on Circuits and Systems (ISCAS), The IEEE Visual Communications and Image Processing Conference (VCIP) and The IEEE International Conference on Multimedia & Expo (ICME). He has chaired special sessions and workshops in ICIP, ICASSP, ISCAS, VCIP and ICME. Prof. Izquierdo has graduated over 30 PhD researchers. He holds several patents in the area of multimedia signal processing and has published over 500 technical papers including books and chapters in books.

Nina Crum - Intel - Hillsboro (USA)
Exploring wacky standard cell architectures with automated gridded design

Abstract:
In physical design, challenges in lithography have been driving more and more design rules that are increasingly more complex and difficult for traditional Electronic Design Automation (EDA) tools to obey. A powerful approach to incorporate any design rule into a placer or router is through gridded design using a SAT solver, where physical objects are mapped to Boolean variables, and the constraints can be modeled as relationships between the variables. In this talk, I will walk through some possible wacky architecture options and show how architecture decisions can be made using SAT-solver-based studies on digital standard cells.

Short Bio:
Nina Lane is a software engineering manager at Intel Corporation in Hillsboro, Oregon. She studied Materials Engineering during her undergraduate and graduate studies, with a BS from UCLA in 2008 and a PhD from Drexel University in 2013. During her PhD, she focused on computational modeling techniques for lattice dynamical behavior of novel materials, spending time at research sites in Sweden, France, and Los Alamos, New Mexico. In her current role at Intel, she manages a group that works in the areas of VLSI and computer-aided design. She develops software engines used to come up with new designs for future Intel technologies, which continuously enable the fabrication of smaller and smaller devices with gains in power and performance. She is heavily involved in efforts to promote diversity and inclusion at Intel, with several campus and conference visits to recruit diverse candidates and give seminars on challenges stemming from gender inequalities in the tech industry.

Laurent Artola - ONERA - Toulouse (France)
An overview of the effect of natural radiation environments on microelectronics

Abstract:
It will be presented an overview of the effect of natural radiation environments on microelectronics. He will first discuss on the description of radiation environment, from space down to the ground. Next, he will present the challenge of reliability induced by radiation in the very large scale interaction roadmap. The punctual effects, called Single Event Effect (SEE) will be addressed. In a third section, he will talk about cumulative effects induced by radiations particles in the microelectronic devices. The similarity between dose effects and aging will be also discussed. Finally, in the last session, the prediction methodologies used to investigate the sensitivity trends of Single Event Effect will be presented with the aim to assess, and to harden new promising technologies, devices and systems for embedded applications.

Short Bio:
Laurent Artola (MSEE 2007, Ph.D. EE 2011) is a research engineer at ONERA since 2012. His researches are focus on radiations effects in devices and integrated circuits, modeling and characterization of Single Event Effects and total ionization dose. He received the best ONERA physics PhD award and the best PhD presentation award. He is regularly involved in radiations R&D projects for space applications. He has served the radiation effects and microelectronics reliability communities as reviewers, session chairman, and member of the award comity for the IEEE Nuclear and Space Radiation Effects Conference (NSREC) and Space RAdiation Effects in Components and Systems (RADECS) european conference. Laurent serves as reviewers in more than 10 journals. He has authored and co-authored more than 30 papers, including one best paper award at RADECS conference paper.

Coffee + Poster Session

Omar Neto - UFMG - Belo Horizonte (Brazil)
Thinking About Future Beyond Silicon Computers: The Nanomagnetic Logic Case

Abstract:
Many scientists states that Moore's Law is close to its end. One of the main reasons is the physical limit of silicon transistors miniaturization. There is not yet an obvious successor technology to the currently CMOS logic, but some possible alternatives have been investigated. In this talk we will discuss in details the historical evolution of computer machines until the end of the golden era where software, architecture, implementation and devices could be developed independently. We will discuss some possible alternatives. The Nanomagnetic Logic (NML) case will be discussed in more detail. NML is a spintronic emerging technology that opens some new opportunities. It is transistorless, allows logic and memory integration and presents very low power, making possible the development of truly reversible architectures.

Short Bio:
Omar Paranaiba Vilela Neto received his undergrad degree in Computer Engineering (2003), M.Sc. degree (2006) Ph.D. degree (2009) in Electrical Engineering from PUC-Rio, Brazil. Since 2010, he is a Professor at the Department of Computer Science, Federal University of Minas Gerais (UFMG), Brazil. His main research interests involve Emerging nanotechnologies, nanocomputing and computational nanotechnology . Omar is head of the Nanocomputing and Computational Nanotechnology Laboratory (NanoComp) at the UFMG. Omar is a member of several conference committees, an Associate Researcher of the Brazilian National Research Council and author and co-author of more than 60 publications in scientific journals and conferences.

Monica Pereira - UFRN - Natal (Brazil)
Using adaptability to increase reliability in Multiprocessor Systems-on-Chip

Abstract:
The widespread usage of Multiprocessor Systems-on-Chip (MPSoCs), with dozens or even hundreds of cores, has brought many challenges. Types of cores, communication, memory, programming are some of the topics related to MPSoC design that must be taking into account in order to achieve high performance and meet requirements such as power, energy, area, safety, etc. Besides those aspects, system reliability has been addressed in many MPSoC designs as a key element to enable device's long-term lifetime. As the feature sizes approach their physical limits, the circuit becomes more prone to several types of faults. In order to cope with the high fault rates, including a fault tolerance solution in all devices becomes mandatory. This talk discusses the main challenges in design of reliable MPSoCs, demonstrating how adaptability can be used as a powerful mechanism to provide fault tolerance in different parts of the system, combining hardware and software solutions to meet system requirements and sustain high performance.

Short Bio:
Monica Pereira received her Bachelor degree in Computer Science at Universidade Federal do Rio Grande do Norte (UFRN), Natal/Brazil in 2005. She received a M.Sc. in 2008 also in Computer Science from Universidade Federal do Rio Grande do Norte and Ph.D. degree at Universidade Federal do Rio Grande do Sul, Porto Alegre/Brazil in 2012. She is currently a Professor at UFRN, where she is co-chair of Systems-on-Chip Laboratory (Laboratório de Sistemas em Chip - LASIC) and chair of the Laboratory for Innovation of Systems-on-Chip (Laboratório para Inovação de Sistemas em Chip - LabISiC). She has experience in Computer Science with emphasis in Computer Systems Architecture, working with the topics: embedded systems, fault tolerance, reconfigurable and adaptable architectures, multicore architectures and network-on-chip.

Sylvain Bourdel - Minatec - Grenoble (France)
RF Low Power Technics

Abstract:
Reducing the power consumption of RF front-end is a major issue for the next generation applications such as IOT or 5G. Several approaches are possible at different levels: technological, circuit design or system design. To efficiently reduce the power consumption of an integrated RF-front-end, all these approaches must be considered in a concurrent way. A overview of recent methods used to improve the consumption in RF systems is presented from the technology to the system. At the technological level, we will especially focus on the performances of the FDSOI technology in the context of RF low power. At the building blocks design level, we will present serval methods such as current reuse and subthreshold approaches. A particular focus will be given on design methods for RF circuits by using MOS transistors operating in moderate or weak inversion. Then, new technics at system levels such as wake-up receiver and RF power gating will be presented.

Short Bio:
He received the Ph. D in microelectronics from the National Institute of Applied Science (INSA) of Toulouse in 2000. He was with the LAAS laboratory of Toulouse where he was involved on radiofrequency systems modelling and he was particularly focused on spread spectrum techniques applied to 2.45GHz transceivers. In 2002 he joined the IM2NP in Marseille where he headed with Pr H. Barthélemy the Integrated Circuit Design Team of the IM2NP. He joined in 2013 the Grenoble-INP as a full Professor where he works at the IMEP-LAHC laboratory. He works on RF and MMW IC design and integration. He particularly focus on low cost and low power applications. His area of interest also includes system level specifications, UWB and RFID. He is the author and co-author of more than 80 referenced IEEE publications.

Ebroul Izquierdo - Queen Mary - University of London (England)
Visual Information Retrieval: From Machine Vision to Human Computation

Abstract:
The performance of any visual information retrieval rest in the accuracy of algorithms for image understanding. Here the main challenge is to overcome the disparity between low-level image features and the richness of semantics in user interpretations of digital images: The semantic Gap. This talk illustrates important technological developments that have contributed to narrowing the semantic gap over the last few years. It will also outline remaining critical challenges in automatic image understanding. Specific successful models to tackle these challenges will be shown in the context of key cutting-edge visual information retrieval applications.

Short Bio:
Ebroul Izquierdo, PhD, MSc, CEng, FIET, SMIEEE, MBMVA, is Chair of Multimedia and Computer Vision and head of the Multimedia and Vision Group in the school of Electronic Engineering and Computer Science at Queen Mary, University of London. Prof. Izquierdo is a IET Chartered Engineer, a member of the Visual Signal Processing and Communications Technical Committee of the IEEE Circuits and Systems Society and member of the Multimedia Signal Processing technical committee of the IEEE. He has been associated editor of the IEEE Transactions on Circuits and Systems for Video Technology (from 2002 to 2010), the IEEE Transactions on Multimedia (from 2010 to 2015). He is member of the editorial board of the EURASIP Journal on Image and Video processing (from 2004 to date) and several other international journals in the field. Prof. Izquierdo has been member of the organizing committee of several conferences and workshops in the field of image and video processing including The IEEE International Conference on Image Processing (ICIP), The IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), The IEEE International Symposium on Circuits and Systems (ISCAS), The IEEE Visual Communications and Image Processing Conference (VCIP) and The IEEE International Conference on Multimedia & Expo (ICME). He has chaired special sessions and workshops in ICIP, ICASSP, ISCAS, VCIP and ICME. Prof. Izquierdo has graduated over 30 PhD researchers. He holds several patents in the area of multimedia signal processing and has published over 500 technical papers including books and chapters in books.

Volnei Pedroni - UTFPR - Curitiba (Brazil)
The Art of Designing and Implementing Finite State Machines in Hardware

Abstract:
A topic with which a digital designer at VLSI level is inevitably faced, particularly in large/complex designs, is the need for and correct implementation of finite state machines (FSMs) in hardware (as opposed to software). This is aggravated by the fact that electronic design automation (EDA) tools are not able of automatically discerning when this approach would be advantageous over others, let alone do the proper system splitting and subsequent optimal or near optimal implementation. The first point discussed is what really differentiates one FSM from another as far as hardware is concerned. It is shown that any FSM falls in one of just three categories, called regular, timed, and recursive finite state machines. This led to the development of three systematic design procedures, allowing any FSM to be easily and optimally implemented in hardware. Other fundamental hardware aspects are treated subsequently, including state encoding styles, input signals conditioning, multiple clock domains and the use of synchronizers, capture of initial values, the importance of reset, the construction of safe state machines, and others. VHDL and SystemVerilog codes for the synthesis of FSMs in all three categories are briefly discussed.

Short Bio:
Volnei Pedroni earned his BSc degree from Federal University of Rio Grande do Sul (UFRGS), and his MSc and PhD degrees from the California Institute of Technology (Caltech), all in Electrical Engineering, with emphasis on analog/digital VLSI design during the PhD. In 2015-16, he did Post-Doctoral work, again at Caltech, with emphasis on analog VLSI for bioengineering. He is a full Professor of Electronics Engineering at the Federal Technological University of Paraná State (UTFPR). He has authored three books published by MIT Press and another published by Elsevier Morgan Kaufmann, all related to the field of Electrical Engineering, and a number of refereed articles in international journals and conferences. He acted as a visiting professor at Caltech, Harvey Mudd College, and University of Trento (Italy).