José M. de la Rosa - Instituto de Microelectrónica de Sevilla (IMSE-CNM) - Sevilla, Spain
Next-Generation Sigma-Delta Converters: Trends and Challenges in a Digital-Driven World

Abstract:
This lecture presents an overview of emerging circuits and systems techniques, which are at the forefront of the state of the art in Sigma-Delta Modulators (ΣΔMs), giving rise to a new generation of data converters that will enable an efficient implementation of the so-called software-defined-electronics paradigm. A number of trends, design challenges and new approaches – like RF/GHz-range ΣΔ digitization in wireless transceivers,digital-assisted analog circuits, time/frequency-to-digital conversion and hybrid ΣΔ/Nyquist-rate Analog-to-Digital Converters (ADCs) – are discussed, as well as the implications derived from their integration in deep nanometer CMOS technologies. Main limitations and problems faced by cutting-edge designs are identified, giving a didactic explanation of them, well supported by an exhaustive statistics-based analysis of over 500 outstanding ΣΔM Integrated Circuits (ICs) in the frontiers of data conversion. Main tendencies, research opportunities and perspectives on the evolution of data converters are envisioned, highlighting how ΣΔM-based analog/digital interfaces can improve their performance and efficiency in an increasingly digital-driven world.

Short Bio:
José M. de la Rosa received the M.S. degree in Physics in 1993 and the Ph.D. degree in Microelectronics in 2000, both from the University of Seville, Spain. Since 1993 he has been working at the Institute of Microelectronics of Seville (IMSE), which is its turn part of the Spanish Microelectronics Center (CNM) of the Spanish Council of Scientific Research (CSIC). He is presently the vicedirector of IMSE and he is also a Full Professor at the Dept. of Electronics and Electromagnetism of the University of Seville. His main research interests are in the field of analog and mixed-signal integrated circuits, especially high-performance data converters, including analysis, behavioral modeling, design and design automation of such circuits. In these topics, Dr. de la Rosa has participated in a number of Spanish and European research and industrial projects, and has co-authored over 220 international publications, including journal and conference papers, book chapters and books. Dr. de la Rosa is an IEEE Senior Member, a Distinguished Lecturer of the IEEE Circuits and Systems Society (term 2017-2018), a member of the Analog Signal Processing Technical Committee of IEEE-CASS, he has served as Chair of the Spain Chapter of IEEE-CASS during the term 2016-2017. He is currently the Deputy Editor in Chief of IEEE Transactions on Circuits and Systems II: Express Briefs and he served as Associate Editor for IEEE Transactions on Circuits and Systems I: Regular Papers, where he received the 2012-2013 Best Associate Editor Award and served as Guest Editor of the Special Issue on the Custom Integrated Circuits Conference (CICC) in 2013 and 2014. He served also as Guest Editor of the Special Issue of the IEEE J. on Emerging and Selected Topics in Circuits and Systems on Next-Generation Delta-Sigma Converters. He is a member of the Steering Committee of IEEE MWSCAS and he has also involved in the organizing and technical committees of diverse international conferences, among others IEEE ISCAS, IEEE MWSCAS, IEEE ICECS, IEEE LASCAS, IFIP/IEEE VLSI-SoC and DATE. He served as TPC chair of IEEE MWSCAS 2012, IEEE ICECS 2012, IEEE LASCAS 2015 and IEEE ISICAS 2018. He has been a member of the Executive Committee of the IEEE Spain Section (terms 2014-2015 and 2016-2017), where he served as Membership Development Officer during the term 2016-2017.

Hai “Helen” Li - Duke University - Durham, NC, USA
Brain Inspired Computing: The Extraordinary Voyages in Known and Unknown Worlds (Part I)

Abstract:
As big data processing becomes pervasive and ubiquitous in our lives, the desire for embedded-everywhere and human-centric information systems calls for an intelligent computing paradigm that is capable of handling large volume of data through massively parallel operations under limited hardware and power resources. This demand, however, is unlikely to be satisfied through the traditional computer systems whose performance is greatly hindered by the increasing performance gap between CPU and memory as well as the fast-growing power consumption. Inspired by the working mechanism of human brains, a neuromorphic system naturally possesses a massively parallel architecture with closely coupled memory, offering a great opportunity to break the 'memory wall' in von Neumann architecture. In this first part of this tutorial, we will start with the evolution of neural networks, followed by the acceleration on conventional platform. I will then introduce the neuromorphic system designs including the approaches based on CMOS and emerging nanotechnologies. The latest research outcomes on hardware implementation optimization, the reliability and robustness control schemes, and new training methodologies by taking the hardware constraints into the consideration will then be presented.

Short Bio:
Hai (Helen) Li received the B.S. and M.S. degrees in microelectronics from Tsinghua University, Beijing, China, and the Ph.D. degreefrom the Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN, USA, in 2004. She is currently an Assistant Professor with the Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA. She was with Qualcomm Inc., San Diego, CA, USA, Intel Corporation, Santa Clara, CA, USA, Seagate Technology, Cupertino, CA, USA, and the Polytechnic Institute of New York University, New York, NY, USA. She has authored and co-authored over 100 technical papers published in peer-reviewed journals and conferencesand holds 67 granted U.S. patents. She has also authored a book entitled "Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing" (CRC Press, 2011). Her current research interests include memory design and architecture, neuromorphic architecture for brain-inspired computing systems, and architecture/circuit/device cross-layer optimization for low power and high performance. Dr. Li was a recipient of the NSF CAREER Award in 2012, the DARPA YFA Award in 2013, and four Best Paper Awards and five best paper nominations from International Symposium on Quality Electronic Design, International Symposium on Low Power Electronics and Design, Design, Automation and Test in Europe, IEEE Computer Society Annual Symposiumon VLSI, Asia and South Pacific Design Automation Conference (ASP-DAC), and International Conference on Computer-Aided Design. She is an AssociateEditor of TODAES and has served as a TPC Member for over 20 international conference series.

Coffee Break + Poster Session 1

Poster Session I Exhibition List:

• AMSyE: An Automated Multi Corner Analysis Environment
  Rodrigo Nogueira Wuerdig, Ney L. V. Calazans and Marcos Luiggi Lemos Sartori
• Initial Detailed Routing Using Regular Patterns
  André Oliveira and Ricardo Reis
• Analysis of the efficiency of Hybrid ATPGs
  Gabriel Porto, Denis Franco and Paulo F. Butzen
• Investigating CMOS Inverters Noise Margins at Different Technologic Nodes
  Clayton Farias and Paulo Butzen
• Evaluating Different 4x4 DST Architectures
  Marcelo Danigno, Rafael Schvittz and Paulo Butzen
• An extension of Fuzzy C-Means applied to detection of cryptographic signatures on DPA/DEMA attacks
  Plínio Finkenauer, Vinícius Camargo, Vitor Lima, Marilton Aguiar and Rafael Soares
• Analysis of VLSI algorithms and circuits for elimination of power line artifacts in EEG signals
  Andrei La Rosa, Pedro Pereira, Sérgio Almeida and Eduardo Costa

Antonio Petraglia - Universidade Federal do Rio de Janeiro (UFRJ) - Rio de Janeiro, RJ, Brazil
Second-Order Analog Filters Having Truly Independent Tunability of Center Frequency and Bandwidth

Abstract:
In many integrated system applications, second-order sections are required as building blocks for the design of higher order filters. In this presentation the designs of second-order analog bandpass and bandstop filters using switched-capacitor techniques to achieve truly independent tunability of center frequency and 3-dB bandwidth will be shown. The filter core is a lattice network that implements a structurally allpass section, in the sense that the transfer function remains allpass regardless of coefficient realization errors produced by fabrication processes. Comparisons with other structures reported in the literature reveals that the proposed filters usually achieve substantially lower capacitance spread and total capacitance, in some cases ten-fold lower, and hence occupies smaller circuit area. A sensitivity analysis verified by circuit simulations shows that the frequency responses of the proposed filters have low sensitivity to capacitance ratio errors.

Short Bio:
Antonio Petraglia received the Engineering and M.Sc. degrees from Federal University of Rio de Janeiro (UFRJ), Rio de Janeiro, Brazil, in 1977 and 1982, respectively, and the Ph.D. degree from University of California at SantaBarbara (UCSB), Santa Barbara, CA, USA, in 1991, all in electrical engineering. He joined the Faculty of UFRJ as a Professorof Electrical Engineering in 1979, where he servedas the Co-Chair of the Department of Electronic Engineering from 1982 to 1984. In 1991, he was a Post-Doctoral Researcher with the Department of Electrical and Computer Engineering, UCSB. He was a Visiting Scholar with the Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, CA, USA, from 2001 to 2002 and with the Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, from 2014 to 2015. He has co-authored a book entitled Stochastic Global Optimization and Its Applications with Fuzzy Adaptive Simulated Annealing (Springer, 2012). His research interests include analog and digital signal processing, and mixed analog-digital integrated circuit design and optimization. Dr. Petraglia was a membr of the Brazilian Microelectronics Advisory Committee of the National Council of Scientific and Technological Development from 2009 to 2012, and the Brazilian Microelectronics Society Board from 2007 to 2011. He served as an Associate Editor of IEEE Transactions on Circuits and Systems - Part II: Analog and Digital Signal Processing from 2002 to 2003, Analog Integrated Circuits and Signal Processing from 2007 to 2008, and Circuits, Systems and Signal Processing from 2009 to 2014. He was a Distinguished Lecturer of the IEEE Circuits and Systems Society in 2011 and 2012.

José Augusto M. Nacif - Universidade Federal de Viçosa (UFV) - Viçosa, MG, Brazil
Designing and debugging applications for modern CPU-FPGA heterogeneous systems

Abstract:
FPGAS became an interesting option to develop hardware accelerators due to their energy efficiency and recent improvements in CPU-FPGA communication speeds. In order to accelerate the development cycle, FPGA high-level synthesis tools have been developed such as Intel HLS, OpenCL, and OpenSPL. These tools aim to free the designer from having to know all the FPGA low-level details. However, in order to achieve high performance processing, the developer should still understand the details of the deeper system layers. In this talk we will present modern heterogeneous CPU-FPGA platforms highlighting the challenges to develop high-performance and energy-efficient accelerators. Moreover, we present an academic tool developed in our research group to generate high-performance, energy-efficient dataflow accelerators for modern CPU-FPGA heterogeneous systems. Finally, we discuss new debug possibilities for these systems and present future research directions.

Short Bio:
José Augusto M. Nacif received the M.Sc. and D.Sc. degrees in computer science from Federal University of Minas Gerais. He is currently an Associate Professor with Universidade Federal de Viçosa (UFV). His areas of interest are Internet of Things, embedded systems, and reconfigurable computing.

Robson Nunes de Lima - Universidade Federal da Bahia (UFBA) - Salvador, BA, Brazil
RF Active Quasi-circulators and their Applications

Abstract:
A circulator is a three-port nonreciprocal device, which transmit a signal injected in one port toward the next port, in only one direction, while isolating it from the remaining other ports. A Quasi-circulator is a similar device with the exception that two of its ports are isolated from each other in both signal flow directions. That is, the signal will be transferred from port 1 to port 2, and from port 2 to port 3, but no signal will flow between ports 3 and 1. Usually, circulators are based on ferrite material whose transmission coefficient is not the same for different directions of propagation. Despite some advantages, such as high-power handling capability and low insertion loss, ferrite passive devices are difficult to be integrated into monolithic circuits. Active circulators were firstly introduced in 1965 by Tanaka, and since then, a number of active quasi-circulator topologies, exploring the nonreciprocal behavior of the transistors, have been presented in literature. In most of the integrated active quasi-circulator devices, the isolation between transmitter (TX) and receiver (RX) ports, on the transmission path, is achieved through a combination of non-reciprocal unilateral devices and power dividers, power combiners and phase shifters. A quasi-circulator can be used, among so many other applications, to couple a transmitter and receiver to a common antenna. In this presentation, I will show a theoretical overview of active quasi-circulators, present different topologies of this device and a number of applications of it, including those related to 5G Full-Duplex Transceivers.

Short Bio:
Robson Nunes de Lima concluiu o Doutorado em Eletrônica e Telecomunicações na École Nationale Supérieure de Télécommunications-ENST-Paris em 2001 e um Pós-Doutorado na Carleton University-Canadá em 2009. É professor associado III da Universidade Federal da Bahia. Sua área de pesquisa está associada à Concepção e implementação de Circuitos Integrados e Híbridos aplicados à interface radiofrequência de transceptores para telecomunicações. Atualmente, coordena o projeto de pesquisa intitulado: Transceptores RF Full-Duplex, financiado pelo CNPq. É membro do Instituto Nacional de Ciência e Tecnologia-INCT-NAMITEC, no âmbito do qual coordena o projeto Transceptores RF para Curtas distâncias.

Coffee Break + Poster Session 2

Poster Session II Exhibition List:

• Cryptography in FPGA by synchronization of chaotic neural networks simulating signals generated by the human body
  Elias de Almeida Ramos, João Carlos Brito Filho and Ricardo Reis
• MPVue - Multi-Processor System-on-Chip Platform for Computer Vision Applications
  Gustavo Ilha, Anderson da Silva, Rafael Viana, Douglas Lawisch, Eduardo da Costa, Davi Lazzarotto, Cezar Reinbrecht and Altamiro Susin
• Ethernet Module for the MPVue : A Computer Vision NoC based Multiprocessor
  Douglas Frantz Lawisch, Gustavo Ilha, Anderson da Silva, Rafael Viana, Eduardo da Costa, Davi Lazzarotto, Cezar Reinbrecht and Altamiro Susin
• Evaluation of legalization algorithms information on submission
  Jorge Ferreira, Paulo Butzen and Cristina Meinhart
• Exploring Approximate Memories in High Efficiency Video Coding
  Ana Mativi, Dieison Silveira and Sergio Bampi
• An Investigation of Security-aware Strategies against Differential Power Analysis
  Vinicius Geraldo, Mateus Brugnaroto, Vitor Lima, Plínio Finkenauer, Vinicíus Camargo and Rafael Soares
• Register File Selective Hardening for Graphics Processing Units
  Jose Rodrigo Azambuja, Fernando Fernandes dos Santos, Marcio Gonçalves, Paolo Rech and Ivan Peter Lamb

Hai “Helen” Li - Duke University - Durham, NC, USA
Brain Inspired Computing: The Extraordinary Voyages in Known and Unknown Worlds (Part II)

Abstract:
As big data processing becomes pervasive and ubiquitous in our lives, the desire for embedded-everywhere and human-centric information systems calls for an intelligent computing paradigm that is capable of handling large volume of data through massively parallel operations under limited hardware and power resources. This demand, however, is unlikely to be satisfied through the traditional computer systems whose performance is greatly hindered by the increasing performance gap between CPU and memory as well as the fast-growing power consumption. Inspired by the working mechanism of human brains, a neuromorphic system naturally possesses a massively parallel architecture with closely coupled memory, offering a great opportunity to break the 'memory wall' in von Neumann architecture. In the second part of this tutorial, new applications and challenges raised in deep learning and neuromorphic computing will be discussed.

Short Bio:
Hai (Helen) Li received the B.S. and M.S. degrees in microelectronics from Tsinghua University, Beijing, China, and the Ph.D. degreefrom the Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN, USA, in 2004. She is currently an Assistant Professor with the Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA. She was with Qualcomm Inc., San Diego, CA, USA, Intel Corporation, Santa Clara, CA, USA, Seagate Technology, Cupertino, CA, USA, and the Polytechnic Institute of New York University, New York, NY, USA. She has authored and co-authored over 100 technical papers published in peer-reviewed journals and conferencesand holds 67 granted U.S. patents. She has also authored a book entitled "Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing" (CRC Press, 2011). Her current research interests include memory design and architecture, neuromorphic architecture for brain-inspired computing systems, and architecture/circuit/device cross-layer optimization for low power and high performance. Dr. Li was a recipient of the NSF CAREER Award in 2012, the DARPA YFA Award in 2013, and four Best Paper Awards and five best paper nominations from International Symposium on Quality Electronic Design, International Symposium on Low Power Electronics and Design, Design, Automation and Test in Europe, IEEE Computer Society Annual Symposiumon VLSI, Asia and South Pacific Design Automation Conference (ASP-DAC), and International Conference on Computer-Aided Design. She is an AssociateEditor of TODAES and has served as a TPC Member for over 20 international conference series.