72 Graduates of CI-INNOVATOR UFRGS phase 1 will present their final projects on April 24 and 25, 2025 at the UFRGS Institute of Informatics. On these days, a Job Fair will be held with the presence of the main semiconductor companies in Brazil.
- Analog and Mixed Signals (AMS)
- Digital
- Management and entrepreneurship in microelectronics
- Radio Frequency (RF)
Analog and Mixed Signal (AMS)
Adriano Miguel Yock Correia
Work Title: A two-stage inverter-based amplifier for medical applications
Abstract: Healthcare devices are pivotal for personalized care, particularly in monitoring ECG signals. This work explores a fully differential instrumentation amplifier in 45-nm CMOS, employing a current-reuse technique to enhance efficiency and noise performance. Presenting the analog front-end architecture, inverter-based topology, design methodology, and simulation-based validation, addressing the challenges of reliable ECG signal processing.
Poster: https://drive.google.com/open?id=1bqL57dgMdknqw6JfwAZJa_vZ1XnkIR4u
LinkedIn: http://www.linkedin.com/in/adrianoyock
GitHub: N/A
Alex Muniz da Costa
Work Title: Design of a Spiking Neuron for Neuromorphic Applications
Abstract: This work presents the design and implementation
of a Leaky Integrate-and-Fire (LIF) neuron for neuromorphic
applications, using 45 nm CMOS technology. The LIF model
mimics the behavior of biological neurons by accumulating
charges until a threshold is reached, at which point it emits a
pulse (spike) and resets its state. The proposed circuit consists of
five main blocks: a leakage circuit (leaky), a membrane capacitor,
a reset circuit, a Schmitt Trigger comparator, and an inverter
to generate the output pulse. The design was optimized for low
power consumption and reduced area, resulting in a total area
of 25.2 µm² and an average consumption of 4.92 pJ per spike —
a competitive value compared to similar works in the literature.
Simulations confirmed the expected functionality of the circuit,
validating its potential for integration into scalable and energyefficient neuromorphic systems.
Poster: https://drive.google.com/open?id=1VEnRDrqTQsUNML8gkc9AqFXqqKsT9hE0
LinkedIn: http://www.linkedin.com/in/alexmuniz10
GitHub: N/A
Állan F. G. Ferreira
Work Title: Design and Analysis of a Two-Stage Floating Inverter Amplifier for Σ∆ Modulators
Abstract: This work presents the design and analysis of a two-stage high-gain floating inverter amplifier (FIA) optimized for energy-efficient, high-resolution sigma-delta (Σ∆) analog-to-digital converters. The proposed architecture combines a simple FIA in the first stage with a cascode FIA in the second, achieving high DC gain without requiring external compensation. The amplifier exploits asymmetric reservoir capacitors to dynamically enhance phase margin and ensure stable closed-loop operation. Detailed analysis of the behavior of the transconductance of the FIA is provided, highlighting its strong dependence on reservoir capacitance and weak sensitivity to device sizing. To validate the amplifier in a practical application, a switched-capacitor integrator was implemented in a 45 nm CMOS process as a case study. The amplifier achieved a peak open-loop DC gain of 69.3 dB, while the integrator exhibited an input-referred noise of 1.10 mVrms and consumed 19.32 µW with a 1.1 V supply.
Poster: https://drive.google.com/open?id=1hvWr0ikiSg6eDLb7RsL_JDbW_1EvFPzG
LinkedIn: https://www.linkedin.com/in/allan-ferreira-5b7353171/
GitHub: N/A
Andreza Costa Nascimento
Work Title: Resistorless CMOS Current Reference
Abstract: This work presents the design of a current reference intended for industrial applications. Such circuits are fundamental building blocks in systems that require a stable and accurate power supply, particularly in environments subject to variations in temperature, voltage, and process parameters. The proposed design ensures low energy consumption and is implemented entirely using MOS transistors. It was developed to supply bias current for a Power-on-Reset (PoR) circuit and is intended to be integrated into a Power Management Unit (PMU). Simulation results demonstrate that the circuit meets the defined specifications, including an output current of approximately 140-nA and total current consumption below 1-uA under extreme conditions. Additionally, the temperature coefficient (TC) was around 2000-ppm/°C under typical operating conditions.
Poster: https://drive.google.com/open?id=1vZ1WzqcpO7hHnarGu_RVEVIBv_Fpq10H
LinkedIn: https://www.linkedin.com/in/andreza-nascimento-ce/
GitHub: https://github.com/Andreza-Nascimento
Arthur Kassick Ferreira
Work Title: 10-bit SAR ADC with gpdk045
Abstract: Analog-to-Digital Converters (ADCs) are a fundamental component of signal processing in dig- ital systems. Each application type presents its own specific requirements and limitations for an ADC. One field that has experienced significant growth for many years, and continues to expand, is signal processing in IoT devices. In this context, power consumption is an important parameter when selecting an appro- priate ADC architecture. In this context, the Succes- sive Approximation Register (SAR) ADC represents a promising candidate for low-power applications. This works presents a 10-bit resolution SAR ADC with a 1MS/s sampling rate developed under the gpdk045 technology,as part of the evaluation process of the CI- Inovador course. The ADC has achieved a 9.52 ENOB with a walden FoM of 61.85f
Poster: https://drive.google.com/open?id=1QfkAErcpudRuKjv6ijZbMFyNTLClBh5d
LinkedIn: https://www.linkedin.com/in/arthur-kassick-ferreira-21528a106/
GitHub: N/A
Bianca Coelho
Work Title: Radiation Robustness Assessment of a 45nm StrongARM Comparator
Abstract: This work investigates the radiation robustness of a StrongARM comparator implemented in 45 nm CMOS technology. The design is based on a previously validated 130 nm implementation and was evaluated under both Total Ionizing Dose (TID) and Single Event Effects (SEE). TID simulations demonstrated stable comparator operation up to 20 Mrad(Si), with minimal impact on timing behavior. SEE simulations revealed bitflips at specific sensitive nodes when charge was injected at 125 ns, consistent with previous 130 nm results. The results confirm the circuit’s resilience to radiation effects and highlight its suitability for future radiation-hardened implementations in advanced CMOS technologies.
Poster: https://drive.google.com/open?id=1GFIxk-SYRr-snqJdX3f_ggXEq2fbR9qq
LinkedIn: http://www.linkedin.com/in/bianca-nunes-coelho-engineer/
GitHub: N/A
Caio Junji Kawata Koyama
Work Title: Design of Front-end for biomedical signals in CMOS technology
Abstract: The analog front-end of biomedical devices is responsible for acquiring, amplifying, and filtering of physiological signals before their conversion to the digital domain. These signals, such as electrocardiogram (ECG), electroencephalogram (EEG), and electromyography (EMG), have low amplitude (microvolt to millivolt) and low frequency (hertz to kilohertz). Due to these characteristics, the use of instrumentation amplifiers and filters becomes essential to improve signal quality. This work proposes an adjustable analog front-end using OTAs composed of the following blocks: an adjustable instrumentation amplifier, a digitally reconfigurable passband filter, and a notch filter. The proposed analog front-end allows adjustment of the lower cut frequency from 100 mHz to 50 Hz, and the upper cutoff frequency from 10 Hz to 3 kHz, with a tunable gain range from 1.5 dB to 22.8 dB, with a total power of 91 μW . All circuits were designed using 45 nm technology node and are intended for biomedical signal amplification, featuring tunable characteristics accommodate a variety of application requirements.
Poster: https://drive.google.com/open?id=1z7bQblL-GtxhUKYiDe637vymVBS-YtGa
LinkedIn: https://www.linkedin.com/in/caio-junji-kawata-koyama/
GitHub: N/A
Diego Henrique Nyland
Work Title: Design of a Low Power DC-DC Inductorless Step Up Converter for Energy Harvesting
Abstract: This work presents the design and analysis of a fully integrated, inductorless DC-DC step-up converter, based on switched-capacitor techniques, targeting ultra-low-power intraocular applications. The proposed architecture is adapted from the work of Shih and Otis~\cite{shih2011}, and introduces an auxiliary charge pump to improve overall efficiency. The main converter generates a regulated $\bm{\mathrm{1.2~V}}$ output from a low-voltage source ($\bm{\mathrm{400~mV}}$), using high-voltage clock signals provided by the auxiliary charge pump to enhance charge transfer. The entire control circuitry is powered by the converter itself and includes a start-up sequence based on a voltage reference and a comparator, enabling autonomous operation from ambient light. Key building blocks such as the reference current source, ring oscillator, and four-phase generator were implemented and validated in simulation. The converter can deliver up to ($\bm{\mathrm{10~\mu A}}$) and demonstrates suitability for self-powered biomedical systems.
Poster: https://drive.google.com/open?id=1ksfT2zTeSEkG0BhezzpBGt2LfR5jmHsA
LinkedIn: http://www.linkedin.com/in/diego-nyland
GitHub: N/A
Felipe Avila Silva
Work Title: Fully Differential Amplifier for Electrochemical Analysis in 45nm CMOS Process
Abstract: The presence of heavy metals in aquatic environments is unavoidable, and their detection is essential because of their high toxicity to humans. Detection is commonly performed using a potentiostat, an instrument widely employed in electrochemistry to control the reference potential in electrochemical cells, thereby enabling current measurements associated with redox reactions. However, heavy metal detection demands voltammetric scans with wide excursion ranges, which poses a challenge for single-ended amplifier designs. This work presents the design of a fully differential amplifier implemented in a 45 nm CMOS process, aiming at integration into fully differential potentiostat architectures. Rail-to-rail input and output stages were adopted to ensure high linearity and wide output swing. The results validate the proposed design and are consistent with values reported in the literature.
Poster: https://drive.google.com/open?id=162YQZ6N9fXoqjQhpSlgcpfWG97HFk0_p
LinkedIn: https://www.linkedin.com/in/felipe-avila-silva-251685178/
GitHub: https://github.com/FelipeAvilaSilva
Felipe Nascimento Torres
Work Title: A 8-bit 1–5-MS/s 1V Supply Voltage SAR ADC With Clock Boosting
Abstract: This paper presents the design and implementation of a low-power successive approximation register analog-to-digital converter using a charge-redistribution-based digital-to-analog converter. The proposed architecture employs a dynamic StrongArm comparator and custom latch-based logic to optimize energy efficiency and area. Implemented in 45 nm CMOS technology, the ADC achieves an effective number of bits of 7.875 bits and a power consumption of 676.6 nW at a sampling rate of 1 MS/s, resulting in a state-of-the-art a Figure of Merit of 2.88 fJ/conversion-step. Furthermore, in order to increase the operation speed, a clock boosting technique was employed, resulting on an operation speed of 5M and a figure of merit of 7.131f. Detailed analyses of the DAC, comparator, and control logic are provided, highlighting trade-offs between power consumption, speed, and noise. The results demonstrate the viability of the design for low-power applications, with the DAC and comparator accounting for 55.4% and 28.6% of total power consumption, respectively, while the logical part consumes some 15.9%.
Poster: https://drive.google.com/open?id=1y1WsqAMDlBDsEzfu6aHDDYGAUJC_0Ybl
LinkedIn: http://www.linkedin.com/in/felipe-ntorres
GitHub: N/A
Giordano de Moraes Rossa
Work Title: Design of Buffer Driver and Current Reference for DC-DC Buck Converter Control on SKY130 CMOS Process
Abstract: This work presents the design and implementation of two critical analog control blocks for a CMOS-based DC- DC Buck Converter using the open-source SKY130 process: a modified constant-gm current reference and a non-overlapping buffer driver. The current reference achieves a temperature- proportional output with stable transconductance, enhanced power supply rejection (PSRR = 111 dB), and minimal startup time (3.62 µs). Its robustness was verified across PVT corners and mismatch Monte Carlo simulations. The buffer driver eliminates shoot-through current via a tri-state switching strategy, ensuring reliable operation of the external power stage. Post-layout results confirm functional integrity under practical ramp-input conditions. These blocks form essential building components for scalable analog power management in open-source design flows.
Poster: https://drive.google.com/open?id=1wQooBdl0yDBlzcaE_XkbYd0eZMQ0wLyh
LinkedIn: http://www.linkedin.com/in/giordanorossa
GitHub: N/A
Henrique Beque
Work Title: Voltage Reference and Error Amplifier for Buck Converters in SKY130nm CMOS
Abstract: Abstract—This paper presents the design and implementation of a voltage reference and an error amplifier intended for integration into the control loop of a Buck-type DC-DC converter using the SKY130nm CMOS process. The voltage reference is based on a bandgap topology using BJTs and MOS current mirrors to achieve temperature compensation. The operational amplifier adopts a two-stage Miller-compensated OTA architecture, designed using the gm/ID methodology to optimize performance, stability, and robustness. Simulation results include process and mismatch variation analysis, confirming proper behavior under industrial conditions. Post-layout considerations and practical design limitations in the SKY130 PDK are discussed. The results validate the feasibility of implementing high-precision analog blocks in open-source CMOS technologies.
Poster: https://drive.google.com/open?id=17VOQQP7Gy8BEO9J6jfddKEihdm_QbtxL
LinkedIn: https://www.linkedin.com/in/henrique-beque-8579b1334/
GitHub: N/A
Henrique Conti Floriani
Work Title: Design of a Programmable Gain Instrumentation Amplifier in a 45 nm CMOS process
Abstract: This paper presents the design of a Programmable Gain Instrumentation Amplifier (PGINA) intended for electrocardiogram (ECG) acquisition in wearable biomedical systems. The development flow encompasses requirement specification, analytical modeling, electrical-level simulations, layout implementation, and Process, Voltage, and Temperature (PVT) variability analysis. In the proposed PGINA architecture, the Operational Transconductance Amplifier (OTA) is designed based on the gm/Id methodology to optimize performance, while the programmable gain stage incorporates transmission gate (TG) structures to ensure low on-resistance and minimal signal distortion. Gain control is implemented with 4-bit resolution, enabling linear-in-dB steps up to 30 dB, with bandwidth preserved across all configurations. Post-layout simulations show a maximum Common-Mode Rejection Ratio (CMRR) of 134 dB and an input-referred noise of 85.94 μV/Hz. The amplifier consumes 373 μW from a 1.1 V supply and occupies a total layout area of 0.038 mm2, designed in a 45 nm CMOS process. These results highlight a favorable trade-off among linearity, noise performance, and power efficiency, supporting the suitability of the proposed solution for low-power, hig-fidelity biomedical signal acquisition in portable applications.
Poster: https://drive.google.com/open?id=1AjVZ5otEf7Uh69c7Mc5N0WQTT-jbtloY
LinkedIn: https://www.linkedin.com/in/henrique-floriani/
GitHub: N/A
Iuri Tinti
Work title: Low-Power Ramp Generator Design for Buck DC-DC Converter Using SKY130nm CMOS Process
Abstract: This work presents the design and implementation of a ramp generator for integration into a pulse-width modulation (PWM) controller of a Buck-type DC-DC converter, fabricated in the SKY130 CMOS process. The generator produces a sawtooth waveform with a target frequency of 100 kHz ±5%, spanning from 0.1 VDD to 0.9 VDD. The architecture includes rail-to-rail comparators, an SR latch, and a current-controlled charge/discharge mechanism. Post-layout simulations validate robustness across process-voltage-temperature (PVT) corners. The complete system consumes 31.97 µW and occupies 5,895.97 µm2 , making it suitable for low-power integrated power management applications.
Poster: https://drive.google.com/file/d/1I7j-DsAeKLHs4LMmIeU5QzELl8ZkujlY/view?usp=sharing
LinkedIn: https://www.linkedin.com/in/iuri-tinti-08378a1b7/
Githut: N/A
João Carlos Prats Ramos
Work Title: Sub-65-mV-Supply, Stacked-Inverter Ring Oscillator for Ultra-Low Voltage Energy Harvesting
Abstract: This study proposes the design of a ring oscillator (ROSC) aimed at VLSI applications operating under ultra-low supply voltages. The startup of energy harvesting circuits powered by thermoelectric generators at reduced supply levels presents significant challenges due to the severe energy constraints during the initialization phase. To overcome this barrier, a low-voltage oscillator capable of triggering the startup of a DC-DC converter was proposed. The circuit was developed using a 45 nm CMOS technology, employing the Cadence Generic Process Design Kit (GPDK) and tools such as Cadence Virtuoso for schematic capture, layout design, and project verification and simulation. The proposed oscillator, composed of 11 stages, is capable of operating at a minimum supply voltage of 43 mV, generating a clock signal with a 90% swing relative to VDD from a 65 mV supply, and exhibiting a power consumption of only 28 pW under typical process and temperature conditions. Furthermore, the design occupies a compact area of only 0.001358 mm², making it highly suitable for integration in space-constrained systems.
Poster: https://drive.google.com/open?id=16dVW29XKyqytst6mkzkeL48mb1XTcUPH
LinkedIn: https://www.linkedin.com/in/joao-carlos-prats-ramos/
GitHub: N/A
Julio Cesar Soares Americo Filho
Work Title: A Compact, Low Quiescent Current Power-On Reset Topology Based on a Single Current Reference
Abstract: This work presents a single-reference, current-based Power-On Reset (POR) topology designed for low-power and area-constrained applications. The proposed design introduces a novel mechanism that utilizes a diode-connected pMOS transistor to derive a supply-tracking signal from a supply-independent reference. This approach enables the use of a single current reference while preserving independent control over the high and low trip voltages. The effectiveness of the topology is validated through the implementation of a hard IP in a 45-nm CMOS technology, occupying a compact area of 17.45 × 29.88 µm2 and consuming only 270.5 nA under worst-case conditions. Post-layout simulations confirm the robustness of the design across process, voltage, and temperature (PVT) variations, as well as device mismatch. These results demonstrate the suitability of the proposed POR topology for highly integrated systems requiring minimal power and silicon area.
Poster: https://drive.google.com/open?id=1pYS2IRC1HAah3DBSd60FInI8AfHQGWA1
LinkedIn: nan
GitHub: N/A
Leonardo Gabriel Rodrigues Sarmento
Work Title: Design and Analysis of a Low-Pass Filter for ECG acquisition in 45nm technology
Abstract: The aim of this study was to implement a 4th-order low-pass filter with 250 Hz cutoff frequency for ECG processing using Sallen-Key topology and Butterworth response via Gm/Id methodology. The filter is design to have a DC gain 0 dB and a GBW of 2 MHz or greater. The project followed key development stages: specification definition, theoretical study, characteristic curve simulations, circuit design and analysis, and final layout implementation. The design was implemented using Cadence Virtuoso and 45nm gpdk (generic process design kit) to meet all specifications. The operational amplifier of the circuit achieved a 56.3 dB gain, 82.26° phase margin, and 12.49 MHz GBW. While the filter reached a DC gain of -1.11 dB and a cutoff frequency of 250 Hz.
Poster: https://drive.google.com/open?id=1AoOA8tv5UVXSNNmvpbzoqg1Snilbzw1E
LinkedIn: https://drive.google.com/drive/folders/1nfTdcMy2zZRnOjnl-be93MUWwFtd7RmX?usp=sharing
GitHub: N/A
Lucas Daudt Franck
Work Title: An 8-bit Digitally Controlled Ring Oscillator with Feedback-Enhanced Current Regulation
Abstract: Inverter-based ring oscillators are highly sensitive to power supply variations that cause frequency pushing and phase noise degradation. Conventional supply regulation techniques, such as low-dropout regulators and cascode current sources, often rely on operational amplifiers or require a large voltage headroom, which limits their use in low-power designs. This work presents an 8-bit digitally controlled ring oscillator that employs a feedback-enhanced current regulation scheme to achieve a cascode-like power supply rejection ratio (PSRR) with the headroom requirement of a standard current mirror. The oscillator was designed in a 45 nm CMOS process and operates in the 100–500 MHz range. The proposed regulation technique improves PSRR by 18 dB compared to a basic current mirror, with only a 15% increase in power consumption.
Poster: https://drive.google.com/open?id=1LtItFr7LBa0yXPuOQ4lkZK_BnTZJLYLs
LinkedIn: http://www.linkedin.com/in/ldfranck
GitHub: N/A
Marcos Paim
Work Title: Single-Ended Instrumentation Amplifier for ECG Monitoring
Abstract: This paper presents the design of an instrumentation amplifier (INA) for wearable electrocardiogram (ECG) monitoring systems using 45nm CMOS technology. The INA is designed to achieve high common-mode rejection ratio (CMRR) and robust performance under varying environmental conditions. The design employs a single-ended three-op-amp topology. Simulation and Monte Carlo analysis demonstrate the INA’s performance, achieving a mean CMRR of 98.59 dB in pre-layout simulation. The layout area of the proposed design is 3.327 × 103 μm2 . Post-layout simulations show a mean CMRR of 91.5 dB with a standard deviation of 9.627 dB. Future work will focus on improving CMRR and reducing variability by exploring alternative op-amp topologies and improved layout techniques.
Poster: https://drive.google.com/open?id=13J1hYt44xO7JQvCG6vWIui2GP4_Z72iJ
LinkedIn: https://www.linkedin.com/in/marcos-paim-49b3b8215/
GitHub: N/A
Mariana Bagni
Work Title: VCO Design for a 2.4 GHz Low Power BLE PLL
Abstract: This project describes the design of CMOS complementary cross-coupled LC-based VCO, implemented in 45nm CMOS technology. It prioritizes low power consumption through bias current optimization and simplified circuit topologies. Integrated in a 2.4GHz PLL architecture, operating with less than 1.0mW from a 1.1V supply, the design targets frequency stability and a phase noise of -110dBc/Hz at a 1MHz offset, which requires control of noise sources and tuning elements. The low power design is, therefore, suitable for systems with low-duty-cycle operation, such as Bluetooth Low Energy (BLE) transceivers, being appropriate for IoT applications.
Poster: https://drive.google.com/open?id=1Q8wxF3gFnFIdXhLK3AV0nzSrAXujQ__D
LinkedIn: https://linktr.ee/marianabagni
GitHub: N/A
Natanael R. Bertamoni
Work Title: ADC SAR VCM-based
Abstract: The common-mode voltage switching scheme employs top-plate sampling. During the initial cycle, differential input signals are connected to the top plates of the capacitor arrays, while the bottom plates are connected to VCM. The most significant bit (MSB) is resolved through a comparison performed immediately after sampling, without requiring energy consumption in the capacitor array [1]. Based on the comparator output, the largest capacitor in the top array is either discharged to ground or charged to VREF, while the bottom array undergoes the opposite operation. Compared to conventional switching methods, the VCM scheme achieves the same resolution with half the total capacitance. This 8-bit analog-to-digital converter (ADC), employing the VCM switching scheme, achieves an effective number of bits (ENOB) of 7.85 under worst-case conditions. It operates with a supply voltage of 1.8V in a 180nm process and consumes an average of 31pJ per conversion at 1 MSPS.
Poster: https://drive.google.com/open?id=1o2Js4GQelUZ9M0QElJ9SBMsl0MOHRE3S
LinkedIn: http://www.linkedin.com/in/natanael-bertamoni-a93590167
GitHub: N/A
Raphael Cardoso
Work Title: A Resistorless Low Power Differentiator for Calibration of Energy Harvesting Systems
Abstract: In the context of RF energy harvesting, it is necessary to ensure appropriate matching between the harvester’s antenna and the power source, often unknown. This matching can be improved using capacitive calibration networks, controlled by a system that monitors the derivative of the stored voltage in a capacitor. This requires a low-power differentiator capable of measuring slow charging slopes, on the order of a few V/s. It is not trivial to implement low-power, stable differentiators, as they usually rely on resistors that are large, noisy, or lead to a high power consumption. In this work, we propose a resistorless topology designed to measure small, positive derivatives in the range of 0-2 V/s, with a DC power consumption of 120 nW, occupying 5175 squared microns. Our circuit takes advantage of negative feedback to improve noise performance by 4× and reduce output voltage variation in mismatch by nearly 14× compared to the state-of-the-art. Our circuit also demonstrates a 5× improved resistance to fluctuations in its supply voltage, which are unavoidable in energy harvesting systems, while displaying a 9× better resistance to temperature variations.
Poster: https://drive.google.com/open?id=1b2zW1uusakgMOh0MXqlbu-glVyPwsyvf
LinkedIn: https://www.linkedin.com/in/cardosorapha/
GitHub: https://github.com/cardosorapha/
Renato Longo Makariewicz
Work Title: Design and Analysis of a Capacitive Charge Pump
Abstract: This work focuses on studying and designing a capacitive charge pump DC-DC converter for voltage elevation in radio frequency energy harvesting (RFEH) systems. The study aims to design a Dickson charge pump circuit that meets certain constraints and performance targets using components from the GPDK45 technology library in Cadence. The article begins with a brief overview of RFEH systems, discussing their advantages and challenges. It then explores the operational principles of the Dickson charge pump, detailing its functionality and the key design considerations. The design process includes selecting and sizing MOSFETs and capacitors to optimize voltage gain and efficiency while accounting for the limitations imposed by the manufacturing process. Through simulations conducted in Cadence Virtuoso, the performance of different transistor types and component dimensions is analyzed, allowing for an optimal balance between output voltage, efficiency, and power capability. Results indicate that the designed charge pump can achieve, for a constant input voltage of 0.5 V, an output voltage of approximately 1.48V with an efficiency of 34.8% for low-power applications around 1µW. The peak efficiency of 42.3% is attained at an output power of 2.2µW and an output voltage of 1.24 V.
Poster: https://drive.google.com/open?id=1WMZoUsrv9NtekKLlewVbBh0xM1t3M7iE
LinkedIn: https://www.linkedin.com/in/renato-longo/
GitHub: N/A
Rodolfo Grosbelli Barbosa
Work Title: Random Telegraph Noise-Based True Random Number Generator: Design and Analysis
Abstract: Random Telegraph Noise (RTN) is a significant source of variability in integrated circuits and has become an increasingly critical issue due to device scaling. On the other hand, this phenomenon can be useful as entropy source for True Random Number Generator (TRNG) circuits, thanks to its stochastic nature. This work presents the design of a voltage source using Verilog-AMS in the Cadence Virtuoso software environment to simulate an RTN signal, followed by the development of a TRNG circuit. Subsequently, Monte Carlo simulations were conducted, with RTN parameters serving as controlled variables. The resulting data were analyzed and evaluated the performance of the circuit under varying RTN parameters, processes and temperature conditions, providing insights into its robustness and reliability.
Poster: https://drive.google.com/open?id=1EYvWFDI8jaXen3CHaOePV9msrAuG4NgA
LinkedIn: https://www.linkedin.com/in/rodolfo-grosbelli-barbosa-25176a207/
GitHub: N/A
Thais M. Brollo
Work Title: Design of a multi-stage comparator with offset compensation
Abstract: This paper presents the design of a 4-stage com- parator with offset compensation for a high-resolution successive approximation register (SAR) analog-to-digital converter (ADC). The topology consists in three preamplifiers followed by a Stron- gArm comparator, where the input-referred offset is compensated through the output offset storage (OOS) technique. Designed using GPDK045 technology with 1.8 V devices, the comparator exhibits a 3σ offset of 969 μV without compensation, reduced to 256 μV with OOS applied to the first two stages — a reduction of approximately 73.6%, confirming that the design is suitable to be used in high-resolution ADCs.
CV: https://drive.google.com/open?id=1_YhN5pj3Nsv-37nUmWCCW9OIwKfmF3og
LinkedIn: https://www.linkedin.com/in/thais-marisco-brollo-27b15a14a/
GitHub: N/A
Tiago Augusto Zanin Salvatti
Work Title: Design and Implementation of Topologies for Random Bit Generation Based on RTN
Abstract: This work presents the design and analysis of two topologies for true random number generation based on Random Telegraph Noise using the Process Design Kit Skywater 130nm. Random Telegraph Noise characterized by random fluctuations in MOS transistors was explored as an entropy source for cryptography and security applications. The topologies amplify signals in the micro to millivolt range at frequencies from 0 to 50 kHz using PMOS LVT and NMOS LVT transistors capacitors MiM and polysilicon resistors. Topology 1 uses a voltage comparator with a 1 Hz low-pass filter while Topology 2 employs a 2 Hz high-pass filter both with switched capacitors to minimize area. An OTA Miller amplifier with high gain was implemented. Monte Carlo simulations indicated variations due to mismatch and Random Telegraph Noise tests revealed limited efficiency below 4 mV. Layouts occupied 30297 square micrometers for Topology 1 and 24652 square micrometers for Topology 2 but lack DRC and LVS checks. Results suggest improvements like Gm-C filters with amplifiers in weak inversion cascode amplifier and capacitance reduction. Redoing the layout with DRC LVS and parasitic extraction is recommended for robust generators in critical applications
Poster: https://drive.google.com/open?id=1SElP8imNikdN6Pd-JZFNHQgIjZ5j6DjY
LinkedIn: nan
GitHub: N/A
DIGITAL
Augusto Cezar Boldori Vassoler
Work Title: Design and Synthesis of a Scaled Dot Product Accelerator with an AXI4-Stream Interface
Abstract: The evolution of deep learning architectures has culminated in Transformers emerging as the state of the art for applications such as natural language processing (NLP) and computer vision. Still, the cost of time and energy for processing highlights the need for the use of accelerators. The present project aims to implement a hardware accelerator for one of the elementary units of a Transformer, the Scaled-dot product attention, in order to mitigate this issue. The designed models are integrated with an AXI-Stream communication interface. The solutions were employed on a RTL-GDSII flow, which included functional verification, logical and physical and synthesis. In order to evaluate the implementation, the synthesis were carried out with different values of operand bit width (4,8 and 12), tokens and features (4, 8 and 16), and attention heads (1, 2 and 4). By doing so, it was found that the presented design is sufficiently robust, presenting satisfactory power consumption, area and maximum frequency, which also scale coherently with the variation of the mentioned parameters. Future explorations include the use of approximate multipliers in order to reduce area and power consumption, and exploration of new architectures. Also, it is intended to include the unity in a complete Transformer architecture, in order to evaluate its impact in a complete system.
Poster: https://drive.google.com/open?id=1KY-oOHkL4SMeGXa4EHiR1FfXrhS6MjO6
LinkedIn: https://drive.google.com/drive/folders/11RTLdZq9Ffs7X5pKPjVT9wT7A9G4CY35?usp=sharing
GitHub: N/A
Bruno Zimmer
Work Title: Implementation and Evaluation of two 32-Point Butterfly FFT Accelerators in a RISC-V Core
Abstract: Abstract—This project integrates two 32-point Fast Fourier Transform (FFT) accelerators into the RS5 RISC-V processor, a four-stage pipeline architecture supportingcustom instructions. We evaluate two FFT accelerator designs(one with parallel input/output and another with serial input/output), comparing their performance against a software-based FFT implementation running directly on the RISC-V core. The accelerator operates independently of the processor pipeline, interfacing with a dedicated register bank and triggered via a custom instruction. This instruction facilitates communication between the core, the register bank, and the FFT module. The study encompasses logical synthesis, physical synthesis, and behavioral analy- sis. The execution efficiency achieves a speedup of 2000× from the standard processor, the area utilization shrinks 22-32% using physical optimizations, and power consumption is reduced by ≈ 37% using clock gating. Index Terms—RISC-V, FFT Butterfly, Hardware Acceleration, Logical Synthesis, Physical Synthesis, Cadence
Poster: https://drive.google.com/open?id=1l9AK_9svQrND-XjS2f0gZuDI8UEO6LVh
LinkedIn: https://www.linkedin.com/in/bruno-s-zimmer/
GitHub: https://github.com/BrunoZimmer/
Cícero Zanoni
Work Title: ASIC implementation of an LSTM neural network
Abstract: Neural networks are widely used in various applications due to their ability to learn complex patterns from large volumes of data. The increasing adoption of AI algorithms is primarily attributed to the fact that neural networks can model complex nonlinear relationships between variables, making them ideal for problems where traditional approaches fail to capture data dynamics. In this context, there is a natural demand for solutions that accelerate processing and improve the reliability of the information produced by neural networks. This work presents the development of a Long Short-Term Memory (LSTM) neural network implemented directly in hardware, following a full ASIC design flow. The proposed approach aims to improve energy efficiency and reduce latency in applications that require sequential processing, such as time series forecasting. The LSTM architecture was described in Verilog and organized into functional modules that perform the core operations of the network, including matrix multiplications, nonlinear activations, and data flow control. To validate the approach, the network was applied to the prediction of the closing price of the Bitcoin cryptocurrency and compared to software-based implementations. Despite an average percentage error of 4.38\% compared to CPU and GPU versions, the ASIC solution proved to be highly efficient. The ASIC-based LSTM implementation achieved a 323× speedup in execution time compared to the CPU and GPU software versions. In terms of power, after physical synthesis, the ASIC implementation demonstrated promising results, with a total power consumption of 15.33 mW. The latency per LSTM cell was 95.7 ns, and the maximum throughput achieved was 10.5 Mops/s. The work concludes by emphasizing that, with targeted adjustments, the proposed model can be scaled and adapted to a variety of real-time inference applications.
Poster: https://drive.google.com/open?id=1GeHF2ZjRpMKrLSH_vLCUfrAMoNXKqfLb
LinkedIn: http://lattes.cnpq.br/1168681041599939
GitHub: N/A
Daniel Ceinoti de Almeida
Work Title: Hardware Implementation of an Intra-Frame Prediction Module for the MPEG-5 EVC Standard Using HLS and an ASIC Flow
Abstract: With the advancement of technology, the resolution and quality of videos have increased over the years. It has become necessary to develop more efficient compression techniques to meet the growing demand for high-quality videos. However, alongside the rising demand, the complexity of algorithms has also grown, aiming to compress and reduce the use of transmission bandwidth. With the Vitis HLS tool, it is possible to implement a complex algorithm in the C programming language and perform automatic implementation in equivalent Verilog. The MPEG-5 Essential Video Coding (EVC) compression standard was developed to surpass existing codecs. The goal of this work is to implement the intra-frame prediction module of the MPEG-5 EVC standard using High-Level Synthesis (HLS), integrated into the Cadence ASIC flow, with the Cadence Genus logic synthesis tool and the Innovus physical synthesis tool. The Sky130 PDK was used as the technology node, achieving an estimated power of 9.91 mW, an estimated area of 62.5 μm², and a clock period of 7 ns, thus enabling intra-prediction for Standard Definition (SD) resolution.
Poster: https://drive.google.com/open?id=1DZ5HTea1278_JuLZDCb5YNMAIeu6Ngqu
LinkedIn: https://www.linkedin.com/in/daniel-ceinoti-2336721a4/
GitHub: N/A
Douglas José da Silva Santos
Work Title: AES-128 Cell-Based Designs in 130nm CMOS Technology: from RTL to GDSII
Abstract: This work proposes the implementation of two AES-128 designs developed from the specifi- cation, along with a Verification Intellectual Property. AES-128 operates on a 128-bit data block called the state and a 128-bit key. There are 10 rounds of transformation performed on the state using AddRoundKey, SubBytes, ShiftRows, and MixColumns for encryption, and AddRoundKey, InvSubBytes, InvShiftRows, and InvMixColumns for decryption. The flow of an Application-specific Integrated Circuit is followed, from the Register Transfer Level to the Graphic Design System II (GDSII), using the open-source Process Design Kit SKY130 with a 130nm node, and the digital design route was chosen using Cadence tools. For the encryption design at the fast corner and after routing, the best performance measurements were obtained, with a maximum frequency of 138.388 MHz, power consumption of 36.34 mW, throughput of 1.355 Gb/s, latency of 94.462 ns, and area of 113,114 μm2. Functional and code coverage of 100% was achieved for AES-128. The designs can be used as IPs in a SoC if the constraints are not tight.
Poster: https://drive.google.com/open?id=1ekPFOD0jfqrtCw1eQBENumfpdEK7LKcy
LinkedIn: http://www.linkedin.com/in/douglas-josé-da-silva-santos-0b5250301
GitHub: N/A
Eduardo Milbrath Gonçalves
Work Title: Scalability Analysis of Multicore RISC-V Architectures for ASIC Implementation
Abstract: In this paper, the implementation and scalability of multicore RISC-V architectures for ASIC design are examined, with an emphasis on the trade-offs between performance, power consumption, and area. We implemented single-core, dual-core, and quad-core configurations using the open-source PicoRV32 processor as a baseline. Starting with functional simulation in QuestaSim, the methodology followed a complete digital design flow. Cadence Genus and the Sky130 standard-cell library were used for synthesis, area, power, and timing analysis. Computational efficiency and core scaling were assessed using the CoreMark benchmark. According to our results, the area and power increased almost linearly with the number of instantiated cores. In the quad-core configuration, the synthesized area grew from approximately 67k $\mu$m² in the single-core design to 265k $\mu$m² at quad-core design. Similarly, overall power consumption increased from 1.19 mW to 4.38 mW. A reliable operation at the desired clock frequency was ensured by the timing slack staying within acceptable bounds despite the increase in logic complexity and interconnects. With scalable performance and controlled increases in physical resources and energy consumption, these results show that multicore RISC-V systems are possible for ASIC implementations. For designers looking for hardware solutions that are optimized for high-performance embedded computing applications, the analysis offers insightful information. In future research, clock gating, improved arbitration procedures, and physical design phases such as placement and routing will be investigated.
Poster: https://drive.google.com/open?id=1Ciz8pMghbrrQsDnYEILzCvzXHXX_g1XS
LinkedIn: https://www.linkedin.com/in/eduardomilbrath/
GitHub: N/A
Eric Friedrich
Work Title: VLSI Design of a Fast and Reprogrammable Decision Tree Inference Accelerator
Abstract: Decision Trees (DTs) are widely used machine learning algorithms for classification and regression tasks due to their easy-to-understand structure and low computational complexity. They are especially well-suited for embedded applications, where the environment is resource-constrained so there is a need for energy and area efficiency. Despite their simplicity, the inference phase of DTs can become a bottleneck when implemented in software on general-purpose processors. This challenge motivates the exploration of dedicated hardware solutions to accelerate decision tree classification. This work proposes a reprogrammable hardware accelerator for DT inference, implemented in VHDL, with the goal of enhancing performance and reducing power consumption, as well as evaluating the impact that parallelism has on those metrics and area. The proposed architecture builds upon a previous implementation and introduces improvements for ASIC implementations. Validation was performed using testbenches and Universal Verification Methodology (UVM) framework to ensure functional correctness. Experimental results demonstrate a performance improvement of at least 8×, when compared with a general-purpose CPU, operating at a maximum clock of 100 MHz. When employing the maximum level of parallelism, the accelerator achieved a 25× speedup relative to the software implementation. The synthesized accelerator, using 130nm Sky-Water PDK, consumes 0.99mW for a DT configuration with 3-bit input width and maximum depth of 3, and up to 790.73mW for a 16-bit input width and maximum depth of 12. This work contributes a scalable and energy-efficient solution for real-time embedded AI systems leveraging decision tree models.
Poster: https://drive.google.com/open?id=1oGz8ZnM20aJwYzGna2KNreCq4AsfbWZE
LinkedIn: https://www.linkedin.com/in/eric-friedrich/
GitHub: https://github.com/Eric-Friedrich/DT_hardware_accelerator
Ester Gomes Pais
Work Title: Computer Implementation of a Reverse Subtract and Skip if Borrow Instruction: From RTL to Layout
Abstract: This work aims to synthesize a small one-instruction processor called “Reverse Subtract and Skip if Borrow” as an ASIC. One-instruction processors are popular as architectural exercises and as a test vehicle for new technologies. There are several types of single instruction computers explored in other studies. My work will be to define the “Reverse Subtract and Skip if Borrow” type of processor in Verilog language and synthesize the description in an ASIC flow. I would like to point out that colleagues under the guidance of the same professor will develop different processors, some of them also one-instruction processors.
Poster: https://drive.google.com/open?id=13yTdeUEmRZfX0vvGZJdclxAmLKIYInQ7
LinkedIn: https://www.linkedin.com/in/estergpais/
GitHub: https://github.com/estergp
Guilherme Barbosa Manske
Work Title: Design Synthesis Comparative Analysis of Binary Adders
Abstract: Optimizing adder efficiency is crucial to improving arithmetic units in artificial intelligence hardware, enabling faster and more energy-efficient accelerators. This project explores different adder architectures, including ripple carry adder, carry select adder, carry increment adder, carry skip adder, carry look-ahead adder, and some parallel prefix adders, evaluating their performance based on metrics obtained from logical and physical synthesis. The architectures are implemented in SystemVerilog, allowing the configuration of some design parameters. After the designs are simulated, they undergo the complete logical and physical synthesis process, resulting in the generation of the GDS2 layout. Different methodologies are used to analyze the different adder designs. The methodologies focus on area, time, and for fair comparisons. By comparing metrics such as area, delay, and power consumption, the study aims to identify the most efficient implementations. The insights from this analysis will contribute to future efforts in optimizing efficient arithmetic hardware accelerators.
Poster: https://drive.google.com/open?id=1Rt-8OO_VH98HphCpaVpU-3eWjvtTcn6W
LinkedIn: https://www.linkedin.com/in/gbmanske/
GitHub: https://github.com/gbmanske/Arithmetics
Gustavo Comarú Rodrigues
Work Title: PPA Analysis of a Secure Network Interface to Protect Communication with Peripherals in Manycore Systems
Abstract: The SNIP (Secure Network Interface for Peripherals) is a network interface designed to secure communication between applications and peripherals in manycore systems based on Network-on-Chip (NoC). This interface implements an authentication protocol that prevents malicious applications from accessing sensitive data in peripherals and also prevents malicious peripherals from attacking the manycore system. Since it is a network interface, this module is instantiated multiple times within the system, making it essential to occupy minimal area and be low power. The goal of this work is to synthesize the SNIP and conduct a power-performance-area (PPA) analysis using synthesis and simulation metrics to evaluate this module. If any metric presents excessive overhead, the study will propose optimizations to improve the efficiency of the SNIP.
Poster: https://drive.google.com/open?id=1RELA42JwP74RAfWBh3EH8OC7HSl6-QAU
LinkedIn: https://www.linkedin.com/in/comaru/
GitHub: N/A
Henrique Cardozo das Neves
Work Title: Design and Implementation of a Single-Cycle RISC-V Processor for FPGA
Abstract: This paper presents the design and implementation of a RISC-V single-cycle processor in FPGA (Field Programmable Gate Array), highlighting the open and modular instruction set architecture (ISA) of RISC-V. The single-cycle processor is used for educational applications due to its simple and lean design. The circuit was implemented using the Verilog language in conjunction with the Quartus II and Questasim tools for processor design and testing.
Poster: https://drive.google.com/open?id=1k2YmwqoQ3NcsQL7oXIZj5ZXAkFFZWsih
LinkedIn: https://www.linkedin.com/in/henriquecneves/
GitHub: https://github.com/henriquecdasneves
Hércules Mosley de Araújo Pinheiro Leonel
Work Title: PPA Evaluation of Hardware Accelerated AES Algorithm Using RISC-V ISE
Abstract: RISC-V open architecture and flexibility make it a choice for embedded devices, where efficient encryption is essential for ensuring data security with minimal resource overhead. The objective of this work is to conduct a power- performance-area (PPA) evaluation of the Zkne Instruction Set Extension (ISE) for the Advanced Encryption Standard (AES) algorithm on a RISC-V processor. This evaluation uses synthesis and simulation metrics, including area and energy costs, clock cycles, and performance monitoring registers, to demonstrate efficiency improvements. To analyze the impact of Zkne ISE on encryption and decryption performance, standard and extended implementations of AES are assessed on the RS5 RISC-V, using an optimized AES algorithm with T-tables, together with the Tinycrypt reference software.
Poster: https://drive.google.com/open?id=1EgBfmKDAVMcA-nX5itB356xsoDUN5XHi
LinkedIn: https://www.linkedin.com/in/h%C3%A9rcules-leonel-710a79216/
GitHub: https://github.com/brbrbrkin
Ítala Lorrane Silva Couto
Work Title: Verificação Formal de Circuitos Digitais: Análise Comparativa entre FPV, FEV, ABV e UVM
Abstract: Este trabalho apresenta um estudo comparativo entre técnicas de verificação de hardware formais e baseadas em simulação, aplicadas ao contexto de sistemas digitais. A análise considera as abordagens de Formal Property Verification (FPV), Formal Equivalence Verification (FEV), Assertion-Based Verification (ABV) e Universal Verification Methodology (UVM). Um buffer FIFO (First-In-First-Out) síncrono é utilizado como estudo de caso para explorar a aplicação prática e a eficácia de cada técnica. O estudo destaca os pontos fortes e limitações de cada abordagem segundo critérios como cobertura, custo computacional, escalabilidade, capacidade de depuração e nível de automação. Os resultados indicam que nenhuma técnica é universalmente superior, e que a combinação entre verificação formal e UVM proporciona maior robustez e eficiência no processo de validação. O trabalho também discute avanços recentes na área e a crescente adoção da verificação formal na indústria de semicondutores.
Poster: https://drive.google.com/open?id=1-fIRN5RbMca_kDFSprtvbHJ82wGKdIYf
LinkedIn: https://www.linkedin.com/in/italacouto/
GitHub: https://github.com/itala-lsc/tcc-verification-formal-fifo
Iuri Albandes
Work Title: Designing Approximate Triple Modular Redundancy Adders in 45nm technology
Abstract: This work investigates the integration of approximate 32-bit adders into Triple Modular Redundancy (TMR) architectures as a means to improve efficiency in fault-tolerant digital systems. By replacing two of the three replicated adders with approximate modules, it is possible to significantly reduce area and power consumption. The challenge lies in preserving acceptable levels of correctness and fault masking, especially in scenarios with aggressive approximation. To address this, the study explores a wide design space of ATMR configurations, combining different types of approximate adders and evaluating their behavior through fault injection and full ASIC implementation.
Poster: https://drive.google.com/open?id=1CK7MNCyql-kfygs0K7l39KmCQ-XYtYU1
LinkedIn: www.linkedin.com/in/iurialbandes
GitHub: N/A
Jean Carlo Hamerski
Work Title: Physical Design of Hardware-Accelerated Publish-Subscribe Middleware for Embedded Systems
Abstract: In embedded systems environments, the publish-subscribe communication model is widely adopted for its scalability and decoupling characteristics. This model allows publishers and subscribers to operate independently, without direct knowledge of each other, enhancing system modularity and flexibility. However, purely software-based implementations can encounter performance limitations, especially in resource-constrained environments. This work presents a hardware-accelerated middleware solution, featuring an API tailored for services and applications, implemented on an RS5 (RISC-V based) processor architecture running the Zephyr operating system. A comparative analysis between the proposed hardware-accelerated middleware and a fully software-based solution is conducted to evaluate performance enhancements. Additionally, a logical and physical synthesis of the proposed hardware accelerator was performed following an ASIC design flow to evaluate maximum operating frequency, area, and power consumption across different middleware configurations. Experimental results demonstrated a performance speedup from 11 to 87.3× over the fully software-based solution. The hardware-accelerated middleware also reduced RAM usage by 3.6× and ROM usage by 7%, compared to the software-based version. Logic synthesis in 45-nm technology revealed a maximum operating frequency of up to 290 MHz, with area occupancy ranging from 0.24 mm² to 0.47 mm² and power consumption between 17.5 and 37.5 mW, depending on configuration. These results highlight the efficiency and practicality of hardware-accelerated middleware as a scalable and low-overhead solution for performance-critical embedded applications.
Poster: https://drive.google.com/open?id=1IkT862Hs9ghGfMzfVnlsRTP7jsJAQcSO
LinkedIn: N/A
GitHub: N/A
João Júnior da Silva Machado
Work Title: Evaluating Triple Modular Redundancy in a RISC-V ALU Through an ASIC-Oriented Design Flow
Abstract: This work presents the design, implementation, and evaluation of a fault-tolerant RISC-V RS5 (RV32I) processor core enhanced with Triple Modular Redundancy (TMR), where redundancy is applied to the Arithmetic Logic Unit (ALU). The approach triplicates the ALU and integrates a majority voting mechanism to tolerate single-event upsets (SEUs) and other transient faults without incurring the full cost of replicating the entire processor. The architecture was developed and validated through a complete ASIC design flow, including logic synthesis, floorplanning, placement, clock tree generation, and physical verification using industry-grade EDA tools. Even with full replication of the ALU logic, the overall processor area and power consumption remained within practical limits, and timing closure was preserved, showing that localized redundancy can be effectively integrated without compromising performance targets. To assess fault resilience, a structured bit-level fault injection campaign was conducted across a wide range of instruction and operand combinations, demonstrating strong masking capabilities (90.32%) and reliable detection of unmasked faults. These results confirm that TMR, when applied strategically, offers an effective trade-off between reliability and resource efficiency, making it a viable solution for high-reliability embedded systems. The contributions of this work include a synthesizable, physically validated TMR implementation, along with a lightweight fault injection framework for RTL-level evaluation. Future directions include exploring hybrid redundancy strategies and layout-aware design techniques to further enhance robustness while minimizing area and energy overheads.
Poster: https://drive.google.com/open?id=1wxrDgA6NfaESaJrEMXwCt7C_FQ7F0sYD
LinkedIn: https://www.linkedin.com/in/joaojrmachado/
GitHub: N/A
João Miguel S. Bedin
Work Title: Design of an ASIC IP for Active Noise Cancellation
Abstract: Nowadays, energy efficiency in digital circuits is essential, making developing low-power architectures crucial. Digital Signal Processing (DSP) is a vast application scenario for low-power design techniques. Building an application through an IP is costly but essential for exploring application-specific integrated circuits (ASIC). This work presents a novel Intellectual Property (IP) for Active Noise Cancellation (ANC), applicable to audio devices. The paper explores the complete digital design flow, from a high-level Python model to functional RTL and GDS-II, comparing the results in three different technology nodes (65-nm, 130-nm, and predictive 45-nm technologies). Results demonstrate an efficient circuit regarding the circuit area, power consumption, and processing timing; the resulting cell area ranges from 0.063655 to 0.1287059 mm$^{2}$, with power consumption around 8-40mw for 10Mhz operation frequency. Future work will use approximate computing techniques to focus on real-time dynamic power management for ANC filtration.
Poster: https://drive.google.com/open?id=1WV-6DbeZShaBTdsahraw3d089REkv4a4
LinkedIn: http://www.linkedin.com/in/jmbedin
GitHub: N/A
José Américo Lacerda Félix
Work Title: Multiply and Accumulate VLSI accelerator with an SPI interface
Abstract: Modern computing and communication systems increasingly depend on efficient hardware accelerators to meet the growing demands of applications such as image processing and artificial intelligence. Convolutional Neural Networks (CNNs), in particular, require intensive Multiply and Accumulate (MAC) operations for feature extraction, emphasizing the need for specialized architectures that optimize performance while maintaining energy efficiency. General-purpose processors and conventional hardware often struggle to balance throughput, latency, and power, especially when integrating communication protocols such as SPI. This work presents the design and ASIC implementation of a custom MAC accelerator with an integrated Serial Peripheral Interface (SPI), targeting ultra-low power applications in embedded and edge AI scenarios. The accelerator was developed using a complete RTL-to-GDSII flow and was optimized for reduced latency, area efficiency, and minimal energy consumption. Post-layout simulations validated its compliance with timing constraints and power targets. The results demonstrate the potential of customized hardware solutions for energy-efficient neural network processing in highly constrained environments.
Poster: https://drive.google.com/open?id=1TWDRkqa0DsyBZE1cpo8b90ZLtBBBVy1M
LinkedIn: N/A
GitHub: N/A
Leonardo Nogueira Lindolfo da Silva
Work Title: Hardware DCT accelerator with SPI interface for communication
Abstract: The Discrete Cosine Transform (DCT) is a cornerstone in modern image and video compression standards such as JPEG and HEVC. Its energy compaction property makes it ideal for transforming spatial data into the frequency domain, where high-frequency components can be discarded with minimal visual loss. Despite its efficiency, traditional DCT implementations rely on real-valued multiplications, which significantly increase power consumption and silicon area—two critical constraints in Application-Specific Integrated Circuits (ASICs) and System-on-Chip (SoC) designs. This work presents the development of a low-power and area-efficient IP Core for the 2D DCT, tailored for integration into SoC architectures. The design is based on the Loeffler algorithm and employs a multiplierless approach, approximating multiplications through shift-add operations to minimize hardware complexity. The 2D transform is implemented using two sequential 1D DCT passes with an internal 8×8 transpose buffer, allowing for row-column processing. To facilitate modular integration and serial data input, the architecture includes a standard SPI interface. The IP Core was fully described in Verilog, verified via random stimulus testbenches in QuestaSim, and compared against Octave-based floating-point references. For physical implementation, a complete ASIC flow targeting Skywater’s Sky130 process was followed, including logic synthesis in Cadence Genus and physical layout in Cadence Innovus, achieving timing closure and manufacturing readiness.
Poster: https://drive.google.com/open?id=1SnJX6F45Ki703FaXXFZqyfb4qR1iuT7z
LinkedIn: https://www.linkedin.com/in/leonardo-nogueira-lindolfo-da-silva-114575165/
GitHub: N/A
Leonardo Real
Work Title: Implementation of an ASIC for Monitoring and Diagnostics in CAN Networks
Abstract: This article presents the development of an application-specific integrated circuit (ASIC) designed for mon itoring messages on a Controller Area Network (CAN). The project focuses primarily on the stages of Register Transfer Level (RTL) modeling, functional verification, logic synthesis, physical synthesis, and automatic test pattern generation, using the tools Xcelium, Genus, Innovus, and Modus, respectively. The ASIC is responsible for processing all received CAN messages and identifying those that match predefined patterns. Upon detecting a match, the circuit activates output signals to notify the event. The remainder of the system architecture, including the use of a Raspberry Pi, a CAN transceiver, and a CAN controller (MCP2551 and MCP2515), is used to demonstrate and validate the application of the ASIC developed in this project. The proposed solution is intended to serve as a support tool for embedded software validation, enabling users to configure which CANmessages should be verified during operation—for example, in agricultural machinery. The final layout consisted of 31,502 logic cells, with a total area of 471,781.226 µm². The power report generated by Innovus indicated an estimated consumption of approximately 7.88 mW. In terms of timing, the post-routing analysis reported a slack of 4.372 ps for the critical path under the same func slow operating mode. These results confirm the feasibility of the developed ASIC for real-time monitoring of CAN messages in embedded system applications.
Poster: https://drive.google.com/open?id=1YWnZEnhmyfeJF5NM1Ow2oyFbbXxH-FEl
LinkedIn: https://www.linkedin.com/in/leonardo-sreal/
GitHub: N/A
Leonardo Sebaje da Silva
Work Title: Implementation of a One-Instruction Set SBNZ Processor: Logic and Physical Synthesis
Abstract: This work presents the design and implementation of a one-instruction processor based on the Subtract and Branch if Not Zero (SBNZ) architecture. The processor is described in Verilog HDL and synthesized, targeting both logic and physical levels using the Cadence Genus and Innovus tools. The main goal is to evaluate the simplicity and effectiveness of a minimalist processor for educational and research purposes. Simulation and synthesis results demonstrate correct functionality and show area and timing characteristics after full place and route. The processor supports 8-bit operands and a 256-position instruction memory and follows a synchronous sequential design. This implementation suits ASIC design flows and provides a foundation for exploring design-space trade-offs in reduced-instruction-set architectures.
Poster: https://drive.google.com/open?id=1xNtS4vUr30Pa3tsBlNEmcbbY__khhyzS
LinkedIn: N/A
GitHub: N/A
Lucas Ledoux Martins da Silva
Work Title: RISC-V RVX Core Optimization with Bit Manipulation Extension: From Simulation to Physical Layout
Abstract: This work presents the optimization of the RVX Core, a 32-bit RISC-V microprocessor optimized for embedded systems that implements the essential RV32I instruction set with the Zicsr control extension. The optimization is achieved through the integration of the Bit Manipulation (B) extension and the SkyWater 130nm node technology. This work presents the full ASIC design flow, from the RTL modification to incorporate the new instructions to the physical layout. The design integrates six new custom instructions that are ANDN, ORN, XNOR, PACK, PACKU and PACKH. Those instructions were implemented to enhance performance in applications such as cryptography, data compression and signal processing. Structural and functional verification validated the functionality of the modified design. The logic synthesis was implemented using Cadence Genus and the open-source SkyWater 130nm PDK, followed by the physical synthesis with Cadence Innovus. The customized RVX core (RV32IB) was synthesized and compared to the baseline RVX core (RV32I), showing the impacts of the addition of Bit Manipulation Instructions (BMI) in slack time improvement and higher operation frequency potential, with minimal area and power increase, confirming the viability of BMI integration for performance-critical embedded applications.
Poster: https://drive.google.com/open?id=1bTz6y5Yrr51Htk3p43T944IyA5hKaTqN
LinkedIn: https://www.linkedin.com/in/lucasledoux/
GitHub: N/A
Lucas Pereira do Amaral
Work Title: Design and Implementation of Low Latency and High Throughput FFT and iFFT in SystemVerilog
Abstract: The growing market demand for faster communication, lower latency, and increased throughput has intensified the need for advanced signal processing techniques. Fourier analysis, pioneered by Joseph Fourier in 1822, provides the foundation for frequency-domain processing, which is essential for modern technologies such as 5G NR, and Wi-Fi. The Fast Fourier Transform (FFT) and its inverse (iFFT), built on the Cooley-Tukey algorithm, address these demands by reducing computational complexity from O(N²) to O(N log N), enabling efficient real-time applications.
Poster: https://drive.google.com/open?id=1FNLL7zPNnm7NGslxDPQm9BV_olpNvBT7
LinkedIn: https://www.linkedin.com/in/lucas-amaral-eu/
GitHub: https://github.com/lucaaamaral
Marcelo Almeida da Silva
Work Title: Adapting an RSA Cryptographic Coprocessor Design for Modern FPGA and ASIC Design Flows
Abstract: The development of a digital system often relies on reusing previous designs. In the semiconductor industry,most contemporary projects adapt and integrate existing designs rather than starting from the scratch. This work presents the reuse of an RSA cryptographic coprocessor originally developed in 2004. The design has been updated to align with modern EDA design tools, incorporating an emulation step using the Pitanga Platform from InPlace Design Systems. Key tasks include translating the design from VHDL to Verilog, emulating the translated Verilog design with the Pitanga platform, and verifying and implementing the updated design using a modern ASIC design environment and flow. This approach not only facilitates design modernization, but also reflects the reality of the industry, where adapting legacy designs is a crucial skill for the successful development of complex systems.
Poster: https://drive.google.com/open?id=1-Zd2PEdXMiv0ymJo1Zs9cDS5Fy0RJDo0
LinkedIn: https://www.linkedin.com/in/marcelo-almeida-da-silva-45021a169/
GitHub: https://github.com/inplace-da/rsa
Marina Longo Dias
Work Title: Impact of Radiation-Hardening Techniques in Adders of RISC-V Designed in 45nm and 7nm Technologies
Abstract: This work investigates the selective integration of radiation-hardening inverter topologies into arithmetic circuits and processor architectures, aiming to improve system resilience against soft errors with minimal overhead. Five inverter designs: Standard, Strengthening, Pseudo-Strengthening, Schmitt Trigger and Rad-Hard, were modeled at the transistor level and analyzed through electrical simulations for delay and energy metrics. These inverters were then integrated into full adder cells to evaluate their impact on performance and robustness. The most promising design, Rad-Hard, was further incorporated into the RS5 processor, a RISC-V implementation, and synthesized using both 45nm CMOS and 7nm FinFET technologies to assess its area and power trade-offs. Results indicate that the Rad-Hard inverter introduces only a modest increase in delay and energy at the circuit level, while full processor synthesis shows that the total area overhead remains below 0.03% in both technologies. These findings confirm that targeted use of hardened cells is a viable strategy to enhance robustness in critical datapaths without compromising the overall efficiency of digital systems and with negligible cost in physical resources.
Poster: https://drive.google.com/open?id=10V0x4UrKqq1kuqrWXP1UoG4YcgJLt8f8
LinkedIn: https://www.linkedin.com/in/marinaldias/
GitHub: N/A
Matheus Lemos
Work Title: 7nm Predictive Technology-Based Multi-Height Standard Cell Library: Enhancing Chip Area
Abstract: The continuous scaling of semiconductor technology has increased the demand for high-performance and efficient integrated circuits. Traditional single-height standard cells face limitations in achieving optimal power, performance, and area (PPA) metrics. This paper presents the design of a multiheight standard cell library for 7nm FinFET technology. The proposed solution aims to minimize the number of tracks by exploring the multi-height technique to address challenges such as routing congestion, while providing greater design flexibility and improved area utilization. We designed 16 cells, achieving up to a 50% area reduction compared to a conventional 6-track library. Logic synthesis results using the ISCAS’89 and ITC’99 benchmarks demonstrate area savings of up to 36% over the 6- track baseline. Additionally, the PicoRV32 RISC-V CPU showed a 77% area reduction compared to the same 6-track library, and its ASIC back-end implementation is presented. These findings suggest a promising direction for future standard cell library designs.
Poster: https://drive.google.com/open?id=1gmR_XWpD7pj6SgN9lBMUKjsuyoCpXxNu
LinkedIn: N/A
GitHub: N/A
Murilo Roschildt Perleberg
Work Title: A Dedicated Hardware Design for the VVC Fractional Motion Estimation
Abstract: Digital videos are becoming increasingly present in people’s daily lives. The inter-frame prediction tools supported by video coding standards explore the similarities between different frames, aiming to represent the motion that occurs in the objects of the scene. However, this motion may not be limited to integer positions, and the Fractional Motion Estimation (FME) tool is required to interpolate samples at fractional positions and search for the set of samples that best represent the fractional motion. Therefore, this work presents a dedicated hardware design for the FME of the Versatile Video Coding (VVC) standard. It adopts a set of dedicated Filters to interpolate samples at fractional positions, group those samples to compose fractional blocks, and define the fractional block most similar to the block being processed. The FME hardware design was verified with realistic input samples and for critical scenarios, and the expected behavior was obtained. The physical synthesis was performed for 45nm technology, and the results show a total area equivalent to 196.7k gates NAND2. The results also show that the FME hardware design can process 60fps of FHD 1080p videos while dissipating 25.5mW.
Poster: https://drive.google.com/open?id=17p28hzXrLDgxwRzJA3lJlfbRAaQ49s0U
LinkedIn: https://www.linkedin.com/in/muriloperleberg/
GitHub: https://github.com/mrperleberg
Pedro Henrique Aquino Silva
Work Title: Open-Source Verification IP for AXI-Stream
Abstract: In modern digital Integrated Circuit (IC) design, accessible and reusable verification solutions are paramount, with the Universal Verification Methodology (UVM) being the industry-standard approach for testbenches of complex IP and System-on-Chip (SoC) designs. However, the availability of high-quality VIP remains limited, particularly for open-source silicon and academic projects. In this context, this work presents the development of an open-access UVM Verification IP (VIP) for the AXI-Stream interface in SystemVerilog. The UVM agent, environment and scoreboard presented are reusable and configurable components for verifying RTL designs that utilize the AXI4-Stream, a point-to-point unidirectional protocol for data streams in SoC interconnects part of the ARM AMBA bus standards. The developed VIP was analyzed in a self-checking scenario, where a transmitter agent is directly connected to a receiver agent, and in a case study with an open-source AXI-Stream FIFO IP at the RTL and a gate-level netlist, achieving 100% code and functional coverage in all covergroups defined for verification of protocol compliance.
Poster: https://drive.google.com/open?id=1jBIeC7A8B9n0TvHA8T4L_XahvVwwkcL9
LinkedIn: https://drive.google.com/file/d/1MHbPqZOOOMtLZTEiQGt-47jGOHbc-IxT/view?usp=drive_link
GitHub: https://github.com/phaquinosilva/axistream-uvc
Rafael Linhares Ferreira
Work Title: Hardware Accelerator for Affine Prediction of VVC Video Encoder Using Decision Trees
Abstract: Video coding is essential for the efficient transmis- sion and storage of digital content, reducing the amount of data without compromising quality. Versatile Video Coding (VVC) was developed to improve compression over its predecessors, including new tools such as Affine Motion Estimation, which is used in inter-frame prediction. This work proposes the imple- mentation in hardware of decision trees previously developed in software, aiming to optimize the Affine tool. The approach seeks to accelerate the decision process and reduce the computational load, ensuring greater efficiency in video coding. This is crucial for applications such as streaming, videoconferencing, and high- resolution broadcasts. The synthesized design of the proposed architecture occupies approximately 3.62 μm2, with a total power consumption of 1.18 mW, and meets timing constraints with a positive slack of 3.23 ns when running at 100 MHz, confirming the feasibility of the hardware solution for real-time applications.
Poster: https://drive.google.com/open?id=1Z6ZwjUAhky0MZ-hvfSJrdONOO9SDfSUE
LinkedIn: N/A
GitHub: N/A
Rafael Tavares Guthes
Work Title: Implementação de Pré-processamento de Imagens em FPGA para Detecção de Pupila
Abstract: A qualidade óptica do olho humano é fortemente influenciada pelo tamanho da pupila. Pupilas maiores permitem a entrada de uma maior quantidade de luz, mas podem comprometer a resolução espacial da visão. Em condições normais, o diâmetro pupilar é controlado principalmente pela luminância da região observada, embora também possa ser afetado por fatores como cor, contraste, atenção e aspectos cognitivos. Alterações no tamanho da pupila impactam diretamente as propriedades ópticas do olho e, consequentemente, o processamento visual. Estudos recentes indicam que as características da íris e da pupila podem ser utilizadas para identificar indivíduos sob influência de álcool, uma vez que o consumo de álcool induz alterações fisiológicas visíveis na região ocular. Notavelmente, o aumento do consumo de álcool tem se tornado uma preocupação significativa de saúde pública, contribuindo para diversos acidentes e complicações médicas. A análise da íris, portanto, surge como uma abordagem promissora, embora os métodos tradicionais de detecção frequentemente enfrentam limitações em termos de precisão e velocidade de processamento. Nesse contexto, este trabalho propõe o desenvolvimento de um sistema embarcado em FPGA, projetado em Verilog e implementado por meio do ambiente Vivado, com foco no processamento de imagens faciais. O sistema implementa um pipeline que realiza o redimensionamento da imagem, a segmentação da região ocular e a extração da pupila diretamente em hardware. O uso de FPGA garante alto desempenho, baixo consumo de energia e resposta imediata, permitindo que a imagem processada seja utilizada em aplicações futuras como análise do reflexo pupilar à luz (PLR), identificação biométrica, monitoramento de fadiga e detecção de substâncias em ambientes clínicos ou automotivos.
Poster: https://drive.google.com/open?id=1DugpEIpEP_-JSg1KperivDuRfHbn75w_
LinkedIn: https://www.linkedin.com/in/rafael-tavares-9b5137b3/
GitHub: N/A
Thales Lopes
Work Title: Project of an IP Core for a Digital PID Controller in Verilog
Abstract: This article presents the development of an IP core for a digital PID controller, following the digital systems design flow in microelectronics. The controller was described in Verilog and implements the proportional-integral-derivative control logic with 32-bit arithmetic, using a Han-Carlson prefix adder and a 16×16-bit multiplier based on the Booth algorithm with a pipelined architecture [15]. The block integration was performed through an interface compatible with the Wishbone bus. Testbenches were developed for the control logic and the communication interface, with functional verification conducted using the Xcelium tool, analyzing waveforms. The project went through logical and physical synthesis stages, generating the layout with Cadence Innovus. The results show an area of 6828.030µm, power consumption of 0.611582 mW, propagation delay of 2.438 ns, and slacks ranging from 1.552 ns to-0.075 ns. Although most paths meet timing requirements, negative slacks indicate failures in asynchronous resets, suggesting optimizations such as clock skew adjustments. The work demonstrates the feasibility of the project, highlighting the application of the digital design flow, while also pointing to future improvements to ensure robustness in real-time control applications.
Poster: https://drive.google.com/open?id=1lk8cJ9RqkZUyq01nC_7CDzbd8OvRpxWv
LinkedIn: www.linkedin.com/in/thaleslmatos
GitHub: N/A
Vítor de Melo Mandowski
Work Title: Approximate Adders for Efficient Circuits: Advantages and Limitations Compared to RCA
Abstract: The ripple carry adder (RCA) is an exact adder optimized for power consumption and circuit area. However, its main drawback is the high propagation delay, as the critical path depends on the sequential propagation of the carry through N full adders. In applications that allow some degree of error tolerance, the use of approximate adders based on RCA can bring significant benefits, such as reducing propagation delay, circuit area, and power consumption. Since each approximate adder technique has its advantages and disadvantages, it is essential to evaluate the context of each application. Depending on the specific requirements, one approximation technique may be more suitable than another. This work aims to analyze the advantages and disadvantages of different approximate adder topologies compared to RCA. For this purpose, the topologies were described in Verilog and subjected to both logic and physical synthesis, with the latter providing more realistic results regarding the circuit behavior. The comparison was based on metrics such as circuit area, power consumption, propagation delay, and error rate of each approach. The results showed that more sophisticated techniques like Lower-Part XOR and OR Gating Adder (LXOA) and Lower-Part OR Gating Adder (LOA) exhibit lower error rates but higher circuit area and propagation delay compared to techniques like Lower-Part Truncation Adder (LTA) and Lower-Part Copy Adder (LCA).
Poster: https://drive.google.com/open?id=1wV3GRGgiJ6DwemYnobhX09H-bFyXMV6J
LinkedIn: http://www.linkedin.com/in/vitor-mandowski-085aaa169
GitHub: N/A
Management and Entrepreneurship in Microelectronics
Arthur Venâncio Furtado Fialho
Work Title: COOVER: Microchip Functional Verification Cooperative
Abstract: The goal of this work is to propose an innovative business model for the semiconductor industry: a cooperative for functional verification, capable of organizing the available workforce in Brazil to better meet the demands of microchip design verification. To achieve this, in addition to seeking a new business model that can succeed in its implementation, some advantages and disadvantages of providing semiconductor services as a cooperative are presented, highlighting which stages of the ASIC flow can also benefit from operating within a cooperative model.
Poster: https://drive.google.com/open?id=1kboX9-j8Tfk5MTa88cAAmTjTBIMkUMxd
LinkedIn: http://www.linkedin.com/in/arthurvff
GitHub: N/A
Gabriella Gomes Alves Rodrigues
Work Title: Microelectronics as a Service: A Brokerage-Based Model Connecting SMEs and ASIC Developers
Abstract: The microelectronics sector has shown steady growth, largely influenced by the demand for custom and high-performance alternatives. However, entry into this field is still largely limited to organizations that produce in large quantities, which complicates access for smaller and medium-sized businesses in specific areas, even though they could significantly take advantage of integrated circuits that are still custom-made and further boost the country’s economy. This study presents an initial assessment of the context surrounding these smaller enterprises and proposes a business plan aimed at connecting them with developers of custom ASICs. The goal is to act as a technical and strategic intermediary, simplifying access to microelectronics. For its initial structure, the project applied the early stages of Design Thinking, along with Lean Startup methods and agile methodologies, as a foundation for future validation and development of the plan.
Poster: https://drive.google.com/open?id=1Pim0JfJDx_UHD2TsuDtT5F5mDU_W-2ml
LinkedIn: https://www.linkedin.com/in/gabriella-gomes-4bb142160/
GitHub: N/A
Lucas Casais de Moraes
Work Title: Business Environment and Plan for a BGA Packaging Plant
Abstract: This project aims to present a semiconductor business environment and plan for a BGA IC packaging plant. In its development, will be considered an estimated capacity of 1 million units per month. And it is expected to map all the processes involved between the packaging and testing process; list the necessary machines and materials; calculate an estimate, in order of magnitude, of the CAPEX cost to implement the line; identify the regulatory environment in Rio Grande do Sul state and Brazil, looking for opportunities and advantages of establishing the business here; identify the availability of qualified labor to serve the business; identify geographic characteristics that favor the implementation of the business; and identify logistical advantages of distance, costs, and agreements for transportation and border inspection
Poster: https://drive.google.com/open?id=19u5ku3FT9GRddDO6d7PTwUMLhv1EtadO
LinkedIn: https://www.linkedin.com/in/lucas-casais-de-moraes/
GitHub: N/A
Matheus Rodrigues Sapata
Work Title: Development of a Temperature and Humidity Sensor with LoRa and Low Power for Precision Agriculture
Abstract: The design of a low-power temperature and humidity sensor used for precision agriculture employing longrange LoRa communication is covered in this paper. It integrates recent analog and digital technologies into one chip rather than traditional IoT solutions where both these technologies reside separately which makes it affordable and scalable for the farmers considering the remotest area. This sensor’s unique design delivers high energy efficiency, extended battery lifespan, and strong communication capabilities which makes it perfectly suited for use in sustainable agriculture practices. The paper does not only pay attention to the technical specs but also to the business and market feasibility. As the agriculture sector moves towards data-driven decisions, such a sensor corresponds to the trend towards low-cost and high-performance sensor systems for agriculture applications. The pricing strategy has been developed on the basis of the analysis of scalability of the production, as well as the expected decrease in costs of mass production, so that the sensor remains within the means of every small and medium-size farm, while maintaining high competitiveness in large ones. This study analyses the financial feasibility, versatility, and growth prospects for the sensor within the international precision agriculture marketplace.
Poster: https://drive.google.com/open?id=1UHuuons6ZHKdIlAI6Kuv-mTiWV8Pnnd3
LinkedIn: https://www.linkedin.com/in/matheus-rodrigues-sapata/
GitHub: N/A
Radio Frequency (RF)
Agner Grion
Work Title: Development and analysis of a pseudo-differential inverter-like transconductor
Abstract: The expansion of the Internet of Things (IoT) has been driven by advances in connectivity, miniaturization, and real-time processing. However, as the number of battery-powered devices increases, challenges related to energy efficiency have emerged. This work proposes the design and analysis of a pseudo-differential inverter-like transconductor with programmable gain, implemented using a 45nm digital CMOS Generic Process Design Kit (GPDK). The circuit is intended for use as a gain element in the intermediate frequency (IF) stage of Bluetooth Low Energy (BLE) receivers.
Poster: https://drive.google.com/open?id=1WcObWBJvplzM5nlPg9XbxwsQxAp3p2Md
LinkedIn: http://www.linkedin.com/in/agner-grion
GitHub: N/A
Débora Chamun
Work title: Design of Low Noise Amplifiers (LNA) for LoRa Ground Station Link
Abstract: Communication systems for the Internet of Things
(IoT) are rapidly evolving, integrating already established tech
nologies that end up fostering new applications. In this sense,
IoT with non-terrestrial networks gains attention, as it allows the
formation of radio links in locations without any infrastructure.
Communication occurs through the transmission of data using
the LoRa protocol to low earth orbit satellites, which in turn relay
to ground stations (GS). This work proposes the development
of a Low Noise Amplifier (LNA) that meets the specifications
of the satellite- GS link. The main parameters of the LNA are
evaluated, such as: Noise Figure, linearity, gain, and consumption, in order to meet the link specifications.
Poster: https://drive.google.com/file/d/1NcLwwcrU1wb6VbqsHQoOmADZhT40AYcA/view?usp=drive_link
LinkedIn: https://www.linkedin.com/in/d%C3%A9bora-zenker-075008125/
GitHub: N/A
Gustavo Paz Platcheck
Work Title: Design of a 482-µW Low-Noise Amplifier for Bluetooth Applications
Abstract: This paper presents the study and design of a narrow-band low-noise amplifier (LNA) in 45nm digital CMOS generic process design kit (gpdk). The input matching is performed by utilizing an inductive degenerated common source amplifier with a gate inductor. The cascode technique is adopted to improve the noise figure and isolation of the output of the circuit. The noise figure of the LNA remained under 2.53 dB from 2.4 to 2.5 GHz with minimum value of approximately 2.33 dB. Additionally, a gain and input reflection coefficient with average values of 19.38 dB and -22.22 dB, respectively, are achieved for the 100 MHz bandwidth. The power consumption at 1 V supply voltage is 482 µW.
Poster: https://drive.google.com/open?id=1NFOqWMkdMSqHszmAq2ti-0HI15C0UV2K
LinkedIn: http://www.linkedin.com/in/gustavo-paz-platcheck-6849a0161
GitHub: N/A
Hugo Dias Gilo
Work Title: A 25% Duty-Cycle Quadrature Single-Balanced Passive Mixer for Mixer-First Receivers
Abstract: Mixer-first receivers leverage the mixer’s transparency impedance to achieve frequency reconfiguration and impedance matching for adaptable radio systems operating across wide frequency bands. 1 This work presents a Mixer-First architecture that employs a 4-phase quadrature passive mixer with 25% duty-cycle, integrated with an impedance matching network to provide passive voltage gain. Cadence Virtuoso and the 45nm GPDK were used for simulation. Performance was evaluated under typical operating conditions, temperature, supply and process corners, and through mismatch and process Monte Carlo analysis. The results demonstrate a conversion gain of 13.43 dB, an NF of 6.23 dB an IIP3 of 7.02 dB, an IIP2 of 71.59 dBm, a LO power of 16.9 mW, and an area of 0.093 mm², excluding the amplifier.
Poster: https://drive.google.com/open?id=1DU7WmQVJUz10Rd86BPeKj0CHdBGiRvnv
GitHub: https://github.com/hugodiasg
João Sulzbach
Work Title: Design Tradeoffs of Cross-Coupled Differential-Drive Rectifiers for UHF RF Energy Harvesting
Abstract: Battery-less, passive tags in RFID and WSN systems require energy harvesting in order to power up the main circuits. One of the core blocks in the harvesting system is the RF rectifier, which converts the RF input from the antenna into a DC voltage level for the main circuit to operate. Among the possible implementations of such a rectifier, the cross-coupled differential-drive (CCDD) cell is one of the most widely used in standard CMOS technologies due to its improved sensitivity for low input power. In this work, the working principle of the CCDD cell is explored, describing the most important metrics for energy harvesting. In particular, the design tradeoffs are explored with simulations with the implementation in a 45nm generic process operating at the 900MHz UHF frequency band. Simulation results show there is an inherent tradeoff between the total energy stored at the output capacitor, the start-up behavior, the PCE, and the input impedance.
Poster: https://drive.google.com/open?id=1O_z8cmOUKO-E4Blc3j4lnPB12S1EkRtN
LinkedIn: https://www.linkedin.com/in/joao-sulzbach/
GitHub: N/A
João Wagner Lopes de Oliveira
Work Title: Low Noise Amplifier in 45nm Process for Sub-6GHz Wireless Communication
Abstract: This paper presents a 45nm CMOS inverter-based Low-Noise Amplifier (LNA) for sub-6GHz wireless communication in 5G/6G systems, achieving high linearity (IIP3) and a compact silicon area compared to prior works. Unlike complex noise-canceling topologies, the proposed design employs a single self-biased CMOS inverter with inductive and capacitive feedback, systematically optimized for superior noise figure (NF), linearity, and power efficiency while minimizing area. The transistors operate in strong inversion, and the feedback network is co-designed to ensure broadband input matching without external biasing circuits.
Poster: https://drive.google.com/open?id=1j2Al4KO9Jnd0PY2AvwW7Bnxb-P9Hsekl
LinkedIn: http://www.linkedin.com/in/joao-wagner-lopes-de-oliveira
GitHub: N/A
Juliano Rafael Andrade
Work Title: Design of a Dual-Band Low-Noise-Amplifier Using Current-Reuse Topology for Multi-Standard Wireless Applications
Abstract: This paper presents the design of a Dual-Band Low-Noise Amplifier (LNA) in a 45 nm CMOS process, utilizing a current-reuse topology for multi-standard wireless applica- tions such as Wi-Fi and IoT. Unlike conventional designs optimized for a single fre- quency, the proposed LNA achieves concurrent operation at 2.3 GHz and 5.5 GHz with noise figures of 2.3 dB and 2.4 dB, respectively, and a power consumption of 10 mW from a 1.8 V supply. The design incorporates a dual-resonant input matching network and a transformer-based output network, achieving excellent reverse isolation (S12 < −45 dB) and robust linearity, with input-referred IP3 values of −14.24 dBm at 2.3 GHz and −8.73 dBm at 5.5 GHz.
Poster: https://drive.google.com/open?id=1kObq0YrVvc9Ura-CxFYiLrCS9jKZgkLH
LinkedIn: N/A
GitHub: N/A
Luiz Fernando Bystronski
Work Title: Design of a high-efficiency synchronous rectifier for RF energy harvesting
Abstract: RF Energy Harvesting for Low-Power Tags: Investigating efficient power generation from radio waves (900 MHz) for applications like identification tags. ● PMOS Rectifier-Based System with Voltage Boosting: Proposing and simulating a multi-stage rectifier using PMOS transistors to enhance output voltage without changing impedance matching, achieving less than 50% efficiency at 10 dBm input power.
Poster: https://drive.google.com/file/d/1SdXenRtRwiSKqlGtfTbVHk0E1W38ca9f/view?usp=drive_link
LinkedIn: N/A
GitHub: N/A
Maiky Barreto da Silva
Work Title: A 45nm CMOS RF Power Amplifier for IoT applications based on Bluetooth Low Energy
Abstract: This project presents the development of an RF power amplifier (PA) for Bluetooth Low Energy (BLE) applications using 45nm CMOS technology. The design consists of two main stages: the amplifier driver and the PA. The driver stage, which features a 50 ohm input impedance, receives the GFSK-modulated signal and converts it into a pulsed signal. This signal is then processed by the amplification stage, where the voltage and current gain are boosted. An output impedance matching network ensures optimal power transfer to the antenna. The primary objective is to maximise output power across the standard industrial temperature range (-40 to 85°C) and the Bluetooth frequency band (2.402 to 2.484 GHz). As a secondary objective, the THD was adjusted to be close to Brazil’s Anatel regulatory specifications for spurious emissions out of the band, around 20 dB.
Poster: https://drive.google.com/open?id=1GayOW7ObDbLNKlMKips9kX3WitJ-uLkD
LinkedIn: https://www.linkedin.com/in/maikybarreto/
GitHub: N/A
Marinel Borges almeida
Work Title: Design of a 2.4-GHz low-power Complementary LC Voltage Controlled Oscillator using 0.45μm CMOS Technology
Abstract: This paper presents a simple 2.4 GHz cross coupled complementary (VCO) LC voltage-controlled oscillator with an external 5.1 nH inductor, designed using a 0.045 μm CMOS process. The proposed VCO achieves a simulated phase noise of –121 dBc/Hz at a 1 MHz offset frequency, while its output frequency is tunable from 2.4 to 2.48 GHz, meeting Bluetooth requirements. Some Key metrics include a tuning range of 80 MHz, a phase noise of –118 dBc/Hz at 1MHz were archived in simulations in Cadence Virtuoso.
Poster: https://drive.google.com/open?id=1amkzR4Z0nhYDDtQ_2qKcgP140HCtCNMs
LinkedIn: http://www.linkedin.com/in/marinel-almeida-5873662bb
GitHub: N/A