37 students are currently in PHASE 2 of CI-INNOVATOR at UFRGS divided into 8 groups developing a System-on-Chip (SoC).
| Thais Brollo |
| Henrique Beque |
| Leonardo Sarmento |
| Eric Friedrich |
| Lucas Amaral |
| Daniel Ceinoti |
Business Model summary: PrimeIPs designs and develops low-cost, disposable, energy-efficient, and multifunctional sensor solutions for biomedical and technology applications. We operate under a B2B service model, providing custom IC design services for design houses, biomedical, and tech companies.Our competitive edge lies in technical expertise, cost optimization, and seamless integration, delivering tailor-made, high-performance sensor systems using advanced EDA tools and a highly specialized engineering team.
Technical Summary: The project focuses on developing an interface module to bridge the Serial Peripheral Interface (SPI) and the Advanced Peripheral Bus (APB) for communication with a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The digital component involves designing a SPI Slave Interface, an APB master and Clock Domain Crossing (CDC) modules. The analog centers on the design and implementation of the SAR ADC. This project is being developed with the support of Ensilica.
| Iuri Albandes |
| Marina Dias |
| João Machado |
| Rafael Ferreira |
| Guilherme Manske |
Business Model summary: We offer a robust and highly adaptable RISC-V processor solution, purposefully engineered to improve system reliability through the strategic application of fault-tolerant techniques, including selective fault injection, mitigation, and verification at the RTL level, which can be delivered either as a fully enclosed chip or a bare die, making it ideally suited for integration as a chiplet in complex SoC architectures, and particularly valuable to companies operating in mission-critical environments where system failure is not an option.
Technical Summary: Application of fault tolerance techniques to the RISC-V architecture, using the RVX processor, derived from the RV32I specification, as a reference. Methodologies such as Triple Modular Redundancy (TMR) and targeted fault injection will be employed directly within the processor’s internal modules. The integration of the fault injection mechanism enables the identification of critical regions in the circuit and the validation of mitigation strategies, thereby reinforcing system reliability. The objective is to demonstrate, through benchmarks such as CoreMark, a significant increase in the RVX’s resilience to faults, evidencing its suitability for applications in which system integrity is non-negotiable. As an outcome, a GDSII layout of the RVX processor will be produced, incorporating the fault tolerance techniques duly implemented and validated.
| Állan Ferreira |
| João Carlos Prats Ramos |
| Renato Longo |
| Adriano Miguel |
| Rodolfo Grosbelli Barbosa |
| Júlio Cesar Soares |
| Hugo Dias |
Business Model summary: Design services and Functional Safety (FuSa) consulting for powering the development of analog and mixed-signal ICs.
Technical Summary: Design of a two-channels Analog Front-End (AFE) in a 130 nm process. The AFE includes a Programmable Gain Amplifier (PGA), low-pass filter and a 10 bits 200 kS/s Vcm-based SAR ADC.
| Murilo Perleberg |
| João Miguel Bedin |
| Gustavo Comarú |
Business Model summary: We are a private research and development center that operates as a scientific and technological institution (ICT), providing specialized services, strategic partnerships, and projects. We also connect national industries with global institutes to foster international collaboration. The first partnership and validation are based on our technical project that underpins our initial activities.
Technical Summary: The project aims to develop an AMS (Analog Mixed-Signal) SoC that integrates digital and analog blocks in a single chip. Its digital core, an ASIC based on an open-source RISC-V, will execute control algorithms over external analog signals, acting as a generic accelerator. The architecture includes internal memories, AXI buses, and dedicated peripherals, notably an ADC to convert analog inputs into digital data for processing. The project is carried out in collaboration with Chipus Microelectronics and INESC-ID, combining academic and industrial expertise to advance low-power, high-performance mixed-signal solutions.
| Vítor Mandowski |
| Lucas Casais Moraes |
| Felipe Avila Silva |
| Tiago Zanin |
Business Model summary: An outsourced IC design team focused on addressing the shortage of available workforce when large design companies need to deliver complex projects within challenging time-to-market constraints. We train new professionals using a hands-on approach, ensuring they are prepared to work on real projects from the start. Additionally, we plan to develop a structured training course to further expand skills and meet the growing market demand.
Technical Summary: The digital project features an APB3 bridge interfacing peripheral devices like GPIO with an AXI Lite bus, translating read/write operations for efficient communication in embedded systems. Two analog projects were developed using TSMC 65nm technology. The first, a Low-Dropout regulator, delivers a stable 1V output with minimal temperature-induced variation. The second, a Phase-Locked Loop, generates an adjustable-frequency clock signal.
| Gabriella Gomes Rodrigues |
| José Americo Lacerda Felix |
| Jean Hamerski |
Business Model summary: BENT-VI delivers high-performance, low-latency AI acceleration through a licensable hardware IP-Core and custom boards, targeting industrial OEMs and system integrators with a scalable, service-driven revenue model.
Technical Summary: Development of a convolutional neural network accelerator based on the Eyeriss accelerator with a focus on low power consumption and low latency.
| Ítala Couto |
| Iuri Tinti |
| Giordano Rossa |
| Felipe Torres |
| Pedro Aquino |
Business Model summary: IoTA is a design house specializing in integrated circuit design services for Energy Harvesting applications, focused on solutions for the logistics chain that require sensing (such as food and healthcare).
Technical Summary: Development of flexible, low-cost IPs for Energy Harvesting in IoT logistics, specializing in ultra-low-power management. Current focus: energy harvester, digital impedance calibration module, temperature sensor, and dual-level voltage sensor.
| Gustavo Platcheck |
| Maiky Barreto |
| João Oliveira |
| Henrique Floriani |
| Andreza Costa |
Business Model summary: IPEH has developed a temperature monitoring system consisting of a sensor chip and a low-cost tag that can be applied directly to product packaging or boxes. The solution allows real-time temperature readings and data to be sent to a cloud platform, where it is possible to track history and generate alerts.
Technical Summary: Development of an Ambient IoT Bluetooth system with wireless power transfer. The main objective of the larger project is to develop a low-cost IoT sensor that operates autonomously, without the need for batteries. To do this, the system uses energy collected from a radio frequency transmitter to power its circuits and read environmental sensors, such as temperature and humidity, and transmit this data. The hardware is designed using 65 nm CMOS technology.
INTERNATIONAL MISSION
