To access the general Chip in Bahia program please click here
Tuesday – September 1st
| Tutorials SBCCI / PATMOS / VARI |
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| 08:40 - 10:20 | Low Power Design Essentials Jan Rabaey, University of California at Berkeley - UCB, EUA Room: Fernando Pessoa 2 |
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| 10:40 - 10:20 | Ultra-Low-Voltage (ULV) IC Design: Designing for VDD below kT/q Márcio Cherem Schneider, Universidade Federal de Santa Catarina - UFSC, Brazil Room: Fernando Pessoa 2 |
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| 13:40 - 15:20 | Impact of Low Frequency Noise on the Reliability and Variability of Nano CMOS devices Jalal Jomaah, Institut National Polytechnique de Grenoble - INPG, France; Lebanese University Room: Fernando Pessoa 2 |
3D ICs - Moving from Silicon to Heterogeneous Technologies Maciej Ogorzalek, Jagiellonian University, Krakow, Poland Room: Fernando Pessoa 3 |
| 15:40 - 17:20 | Cyber - Physical Systems: Reality, Dreams, and Fantasy Magdy A. Bayoumi, University of Louisiana at Lafayette, EUA Room: Fernando Pessoa 2 |
Low Loss, High Isolation, Linear RF Switch Design in SOI Peter H. Popplewell, Skyworks Solutions, Canada Room: Fernando Pessoa 3 |
| OPENING Room: Fernando Pessoa 1 and Fernando Pessoa 2 Hour: 18:00 to 18:20 |
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| Cocktail Room: Foyer S2 & Praça Luiz de Camões Hour: 18:40 - 20:00 |
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Wednesday – September 2nd
| Keynote | |
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| 08:00 - 09:40 | Lessons from Brain Connectivity for Future Interconnect in ICs Jan Rabaey, University of California at Berkeley - UCB, EUA Room: Fernando Pessoa 1, 2, 3 |
| Session 1: Circuit and system optimization Room: Fernando Pessoa 3 Chair: Ran Ginosar, Technion-Israel Institute of Technology, Israel |
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| 10:00 - 10:20 | Response Time Schedulability Analysis for Hard Real-Time Systems Accounting DVFS Latency on Heterogeneous Cluster-based Platform Eduardo Bezerra Valentin, Mario Salvatierra, Rosiane Freitas and Raimundo Barreto, (Federal University of Amazonas, Brazil) |
| 10:20 - 10:40 | Inferring Custom Architectures from OpenCL Krzysztof Kepa, Ritesh Soni and Peter Athanas, (Virginia Tech, USA) |
| 10:40 - 11:00 | ABeeMap: A Mapping Algorithm based on Multi-Objective Artificial Bee Colony Viviane Souza and Abel Silva-Filho, (Federal University of Pernambuco, Brazil) |
| 11:00 - 11:20 | Efficient Parallelization of the Discrete Wavelet Transform Algorithm using Memory-oblivious Optimizations Anastasis Keliris1, Vasilis Dimitsas, Olympia Kremmyda2, Dimitris Gizopoulos2, and Michail Maniatakos1, (NYU1, USA and University of Athens2, Greece) |
| 11:20 - 11:40 | Calculation of Worst-Case Execution Time for Multicore Processors using Deterministic Execution Hamid Mushtaq1, Zaid Al-Ars2 and Koen Bertels1, (TU Delft1 and Delft University2, Netherlands) |
| 11:40 - 12:00 | An Unconventional Computing Technique for Ultra- Fast and Ultra-low power Data Mining Vincent Canals, Antoni Morro, Antoni Oliver, Miquel Lleó Alomar and Josep L. Rosselló, (Universitat de les Illes Balears, Spain) |
| Invited Talk | |
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| 13:20 - 14:00 | Frame Free Vision Teresa Serrano-Gotarredona, IMSECNM-CSIC, Sevilla; University of Sevilla, Spain Room: Fernando Pessoa 3 |
| Session 2: System-level design and management Room: Fernando Pessoa 3 Chair: Vincent Canals, Balearic Islands University, Spain |
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| 16:00 - 16:20 | Tejas: A Java based Versatile Micro-architectural Simulator Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel and Eldhose Peter, (IIT Delhi, India) |
| 16:20 - 16:40 | Dedicated Network for Distributed Configuration in a Mixed-Signal Wireless Sensor Node Circuit Soundous Chairat, Edith Beigné and Marc Belleville, (CEA LETI, France) |
| 16:40 - 17:00 | Energy Management via PI Control for Data Parallel Applications with Throughput Constraints Anca Molnos, Warody Lombardi, Diego Puschini, Julien Mottin, Suzanne Lesecq, and Arnaud Tonda, (CEA LETI, France) |
| 17:00 - 17:20 | VLSI Architecture Design and Implementation of a LDPC Encoder for the IEEE 802.22 WRAN Standard Nelson Alves Ferreira Neto1, Wagner Luiz Alves de Oliveira2, João Carlos Nunes Bittencourt3 and Joaquim Ranyere Santana de Oliveira2, (LSITEC-NE1, UFBA2, UEFS3, Brazil) |
| Special Session: Celebrating the 25th Anniversary of PATMOS Room: Fernando Pessoa 3 Chair: Ricardo Reis, UFRGS, Brazil |
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| 17:20 – 18:20 | How to Cope with the Power Wall Reiner Hartenstein, TU Kaiserslautern, Germany |
Thursday – September 3rd
| Keynote | |
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| 08:00 - 09:40 | Majority-based Synthesis for Digital Nano-technologies Giovanni de Micheli, EPFL, Switzerland Room: Fernando Pessoa 1, 2, 3 |
| Session 3: Low power design techniques Room: Fernando Pessoa 3 Chair: Jose Luis Guntzel, UFSC, Brazil |
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| 10:00 - 10:20 | Dynamic Current Reduction of CMOS Digital Circuits through Design and Process Optimization Jordan Innocenti1, Loïc Welter1, Nicolas Borrel1, Franck Julien1, Jean-Michel Portal2, Jacques Sonzogni1, Laurent Lopez1, Pascal Masson3, Stephan Niel1, Philippe Dreux1 and Julia Castellan1, (STMicroelectronics1, Aix-Marseille University2, Nice Sophia-Antipolis University3, France) |
| 10:20 - 10:40 | Unified Power Format (UPF) methodology in a vendor independent flow Emilie Garat, David Coriat, Edith Beigné and Leandro Stefanazzi, (CEA LETI, Minatec, France) |
| 10:40 - 11:00 | Asynchronous Sub-Threshold Ultra-Low Power Processor Ron Diamant1, Ran Ginosar1 and Christos Sotiriou2, (Technion IIT1, Israel, University of Thessaly2, Greece) |
| 11:00 - 11:20 | Constructing Stability-based Clock Gating with Hierarchical Clustering Bao Le1, Djordje Maksimovic1, Dipanjan Sengupta2, Erhan Ergin3, Ryan Berryhill1 and Andreas Veneris1, (University of Toronto1, Canada, Advanced Micro Devices, Inc.2, Canada, AMD3, USA) |
| 11:20 - 11:40 | Adaptive Energy Minimization of Embedded Heterogeneous Systems using Regression-based Learning Sheng Yang1, Rishad Shafik1, Geoff Merrett1, Ed Stott2, Joshua Levine2, James Davis2 and Bashir Al-Hashimi1, (University of Southampton1, Imperial College2, United Kingdom) |
| 11:40 - 12:00 | Evaluation and Mitigation of Aging Effects on a Digital On-Chip Voltage and Temperature Sensor Mauricio Altieri, Suzanne Lesecq, Diego Puschini, Olivier Heron, Edith Beigne and Jorge Rodas, (CEA LETI, France) |
| Invited Talk | |
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| 13:20 - 14:00 | System-Level Design of Heterogeneous System-on-Chip Architectures Luca Carloni, Columbia University, EUA Room: Fernando Pessoa 3 |
| Session 4: Reliability, noise reduction and robustness Room: Fernando Pessoa 3 Chair: Jorge Juan-Chico, Seville University, Spain |
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| 14:00 - 14:20 | Exploration of Technology Parameter Values of Integrated Circuit Technologies Rodrigo Fonseca Rocha Soares1, Frank Sill Torres1,2 and Dirk Timmermann3 (UFMG1, Brazil, DELT2, University of Rostock3, Germany) |
| 14:20 - 14:40 | Frequency-Domain Modeling of Ground Bounce and Substrate Noise for Synchronous and GALS Systems Milan Babic, Xin Fan and Milos Krstic (IHP, Germany) |
| 14:40 - 15:00 | Better-than-Voltage Scaling Energy Reduction in Approximate SRAMs via Bit Dropping and Bit Reuse Fabio Frustaci1, David Blaauw2, Dennis Sylvester2 and Massimo Alioto3, (University of Calabria1, Italy, University of Michigan2, USA, National University of Singapore3, Singapore) |
| 15:00 - 15:20 | A Versatile and Reliable Glitch Filter for Clocks Robert Najvirt and Andreas Steininger, (TU Wien, Austria) |
Friday – September 4th
| Keynote | |
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| 08:00 - 09:40 | A Path towards Average-Case Silicon via Asynchronous Resilient Bundled-Data Design Peter Beerel, University of Southern California (USC) in Los Angeles, EUA Room: Fernando Pessoa 1, 2, 3 |
| Session 5: Energy-efficiency systems Room: Fernando Pessoa 3 Chair: Frank Sill Torres, UFMG, Brazil |
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| 10:00 - 10:20 | Energy-Efficient Level Shifter Topology Roger Llanos, Diego Sousa, Marco Terres, Guilherme Bontorin, Ricardo Reis and Marcelo Johann, (UFRGS, Brazil) |
| 10:20 - 10:40 | Energy efficiency of Zipf traffic distributions within Facebook’s data center fabric architecture Lisa Durbeck1, Nicholas Macias1 and Joseph Tront2 , (Cell Matrix Corporation1, USA, Clark College2, USA) |
| 10:40 - 11:00 | Energy-Aware Mapping for Dependable Virtual Networks Victor Lira and Eduardo Tavares, (Federal University of Pernambuco, Brazil) |
| 11:00 - 11:20 | Reusing Smaller Optimized FFT Blocks for the Realization of Larger Power Efficient Radix-2 FFTs Sidinei Ghissoni1, Eduardo Da Costa2 and Ricardo Reis3, (Unipampa1, UCPel2, UFRGS3, Brazil) |
| 11:20 - 11:40 | Combining Pel Decimation with Partial Distortion Elimination to Increase SAD Energy Efficiency Ismael Seidel, André Beims Bräscher and Jose Luis Güntzel, (UFSC, Brazil) |
| 11:40 - 12:00 | Wideband Dynamic Voltage Sensing Mechanism for EH Systems Kaiyuan Gao1, Yuqing Xu1, Delong Shang1, Fei Xia1 and Alex Yakovlev2 (Newcastle University1, University of Newcastle upon Tyne2, United Kingdom) |
| Invited Talk | |
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| 13:20 - 14:00 | Rethinking "Things" Design - The Missing Technology Link in the Internet of Things (IoT) Massimo Alioto, National Univ. of Singapore Room: Fernando Pessoa 3 |
Important Dates
Final deadline extension
June 6, 2015
Submission deadline
(Regular Papers)
June 6, 2015
Submission deadline
(Special Sessions)
July 6, 2015
Notification of acceptance
July 31, 2015
Camera-ready papers due
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