[7] Contributions to the Evaluation of Ensembles of Combinational Logic Gates
Microelectronics Journal, v.42, p.371-381, 2011.
[6] Standby Power Consumption Estimation by Interacting Leakage Current Mechanisms in Nanoscaled CMOS Digital Circuits
P. F. Butzen, L. S. da Rosa Jr., E. J. D. Chiappetta Filho, D. S. Moura, A. I. Reis, R. P. Ribas
Microelectronics Journal, v.41, p.247-55, 2010.
[5] Gate Delay Variability Model for Parametric Yield Improvement in Nanometer CMOS Technology
D. N. da Silva, A. I. Reis, R. P. Ribas
Microelectronics and Reliability, v.50, p.1223-29, 2010.
[4] Transistor Network Restructuring Against NBTI Degradation
P. F. Butzen, V. Dal Bem, A. I. Reis, R. P. Ribas
Microelectronics and Reliability, v.50, p.1298-303, 2010.
[3] Leakage Analysis Considering the Effect of Intra-Cell Wire Resistance for Nanoscaled CMOS Circuits
P. F. Butzen, A. I. Reis, R. P. Ribas
Journal of Low Power Electronics (JOLPE), v.6, p.192-200, 2010.
[2] Karma: um Ambiente para o Aprendizado de Síntese de Funções Booleanas. (in Portuguese)
C. E. Klock, R. P. Ribas, A. I. Reis
Revista Brasileira de Informação na Educação (RBIE), v.18, p.33-42, 2010.
[1] CMOS Logic Gate Performance Variability Related to Transistor Network Arrangements
D. N. da Silva, A. I. Reis, R. P. Ribas
Microelectronics and Reliability, v.49, p.977-81, 2009
[19] KL-Cuts: A New Approach for Logic Synthesis Targeting Multiple Output Blocks
O. Martinello Jr., F. S. Marques, R. P. Ribas, A. I. Reis
DATE 2010
[18] Boolean Factoring with Multi-Objective Goals
M. G. A. Martins, L. S. da Rosa Jr., A. B. Rasmussen, R. P. Ribas, A. I. Reis
ICCD 2010
[17] Improvements on the Detection of False Paths by Using Unateness and Satisfiability
F. S. Marques, O. Martinello Jr., R. P. Ribas, A. I. Reis
SBCCI 2010
[16] SwitchCraft: a Framework for Transistor Network Design
V. Callegaro, F. S. Marques, C. E. Klock, L. S. da Rosa Jr., R. P. Ribas, A. I. Reis
SBCCI 2010
[15] Efficient Test Circuit to Qualify Logic Cells
R. P. Ribas, S. Bavaresco, M. S. Lubaszewski, A. I. Reis
ISCAS 2009
[14] Switch Level Optimization of Digital CMOS Gate Networks
L. S. da Rosa Jr., F. R. Schneider, R. P. Ribas, A. I. Reis
ISQED 2009
[13] Routing Resistance Influence in Loading Effect on Leakage Analysis
P. F. Butzen, A. I. Reis, R. P. Ribas
PATMOS 2009
[12] Equivalent Circuit for NBTI Evaluation in CMOS Logic Gates
N. Schuch, V. Dal Bem, A. I. Reis, R. P. Ribas
SBMicro 2009
[11] The Impact of CMOS Logic Gate Topologies on Performance Variability
D. N. da Silva, Digeorgia N., A. I. Reis, R. P. Ribas
SBMicro 2009
[10] Speed-up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering
T. Cardoso, L. S. da Rosa Jr., F. S. Marques, R. P. Ribas, A. I. Reis
ISQED 2008
[9] Simple and Accurate Method for Fast Static Current Estimation in CMOS Complex Gates with Interaction of Leakage Mechanisms
P. F. Butzen, L. S. da Rosa Jr., E. J. D. Chiappetta Filho, D. S. Moura, A. I. Reis, R. P. Ribas
GLSVLSI 2008
[8] DAG Based Library-Free Technology Mapping
F. S. Marques, L. S. da Rosa Jr., R. P. Ribas, S. Sapatnekar, A. I. Reis
GLSVLSI 2007
[7] Modeling and Estimating Leakage Current in Series-Parallel CMOS Networks
P. F. Butzen, A. I. Reis, C. H. Kim, R. P. Ribas
GLSVLSI 2007
[6] Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates
P. F. Butzen, A. I. Reis, C. H. Kim, R. P. Ribas
PATMOS 2007
[5] A Comparative Study of CMOS Gates with Minimum Transistor Stacks
L. S. da Rosa Jr., F. S. Marques, F. R. Schneider, R. P. Ribas, A. I. Reis
SBCCI 2007
[4] Fast Disjoint Transistor Networks from BDDs
L. S. da Rosa Jr., F. S. Marques, T. Cardoso, R. P. Ribas, S. Sapatnekar, A. I. Reis
SBCCI 2006
[3] CMOS Logic Gates Based on the Minimum Theoretical Number of Transistor in Series
F. R. Schneider, A. I. Reis, R. P. Ribas
NORCHIP 2006
[2] A New Approach to the Use of Satisfiability in False Path Detection
F. S. Marques, R. P. Ribas, S. Sapatnekar, A. I. Reis
GLSVLSI 2005
[1] Exact lower bound for the number of switches to implement a combinational logic cell
F. R. Schneider, R. P. Ribas, S. Sapatnekar, A. I. Reis
ICCD 2005