BIO: is currently the John O'Hara Associate Professor of Electrical Engineering at the University of Notre Dame. She obtained B.S. in physics from Peking University (1996), M.S. in Material Science from Lehigh University (1998) and Ph.D. in Electrical Engineering from University of California, Santa Barbara (2003), respectively. Her research focuses on development of III-V nitride and 2-D crystal semiconductor growth, electronic and optoelectronic devices, especially the interplay between material properties and device development. More recent research interests include THz applications. She is a recipient of AFOSR Young Investigator Award and NSF CAREER Award.

ABSTRACT: In the first half of the talk, I will review the recent development of tunnel field effect transistors (TFETs) [1]. Tunnel FETs are promising replacements of Si-MOSFETs beyond 2020 due to their promise to achieve Ion/Ioff > 103 with Ion > 100 uA/um at low supply voltages (up to 0.5 V). To date we have demonstrated Ion/Ioff ~ 106, Ion ~ 180 uA/um, separately. Challenges ahead include electrostatic control, defect-assisted tunneling and interface state density and parasitics.
In the second half of the talk, I will review our current research topics on GaN electronics include high-speed transistors, power switches, and THz devices [2].
If time allows, I will briefly discuss our work on graphene.  Graphene, an atomically thin 2D crystal with zero bandgap, has been touted for many intriguing applications, particularly for transparent touch screens and wearable electronics.  Its optoelectronic properties are equally noteworthy.  We successfully constructed THz modulators using graphene for the first time, another new avenue for graphene research [3].

[1] InGaAs/InP tunnel FETs with a subthreshold swing of 93 mV/dec and 106 on/off current ratio.  & GaSb/InAs tunnel field-effect transistor with on-current of 180 uA/um at 0.5 V.  G. Zhou, A. Seabaugh and H. G. Xing et al.  IEEE Electron Device Letters and IEDM 2012.
[2] a) Polarization-induced hole doping in wide-band-gap uniaxial semiconductor heterostructures.  John Simon et al.  Science 327, 60 (2010).  b) InAlN/AlN/GaN HEMTs with regrown ohmics and fT of 370 GHz. Yuanzheng Yue et al. IEEE Electron Device Letters, 2012.  c) Power gain at THz frequencies via plasma wave excitations in HEMTs exhibiting gate negative differential conductance. Berardi Sensale-Rodriguez et al. 2012.
[3] a) Broadband graphene terahertz modulators enabled by intraband transitions.  B. Sensale-Rodriguez et al.  Nature Communications, 2012.  b) Extraordinary control of terahertz beam reflectance in graphene electro-absorption modulators.  B. Sensale-Rodriguez et al.  Nano Letters, 2012.

BIO: received the M.S. and Ph.D. degrees in Computer Science from the Universitat Politecnica de Catalunya, Barcelona, in 1985 and 1987, respectively. He is a Professor in the Department of Software of the same university. In 1988, he was a Visiting Scholar at the University of California, Berkeley. His research interests include formal methods and computer-aided design of VLSI systems with special emphasis on asynchronous circuits, concurrent systems and logic synthesis. He has co-authored numerous research papers and has been invited to present tutorials at various conferences. Prof. Cortadella has served on the technical committees of several international conferences in the field of Design Automation and Concurrent Systems. He received best paper awards at the Int. Symp. on Advanced Research in Asynchronous Circuits and Systems (2004), the Design Automation Conference (2004) and the Int. Conf. on Application of Concurrency to System Design (2009). In 2003, he was the recipient of a Distinction for the Promotion of the University Research by the Generalitat de Catalunya.

ABSTRACT: This seminar will cover the fundamental aspects and some advanced topics on the design of elastic circuits. There will be two main parts:

I - Asynchronous circuits
II - Synchronous elastic circuits

The first part will review the fundamentals of asynchronous circuits, including asynchronous communication mechanisms, handshake protocols, pipelines and Globally-Asynchronous Locally-Synchronous systems. Logic synthesis techniques for asynchronous controllers and synthesis from high-level languages will also be presented.

The second part will introduce timing elasticity in synchronous circuits (latency insensitivity). Techniques for design automation and performance analysis of elastic circuits will be discussed. The seminar will conclude with some advanced techniques for architectural optimization and the discussion of open research topics on elastic circuits.

BIO: is a Principal Scientist at imec, Belgium. He received the M.S. degree in Physical Electronics from Charles University, Prague, in 1992 and the M.S. and Ph.D. degrees in Physics from The Ohio State University, in 1996 and 1998, respectively. In 1998 he joined the reliability group of imec. He has co-authored more than 300 journal and conference papers, presented a number of invited papers and tutorials at international conferences, and received 5 IEEE IRPS Best or Outstanding Paper Awards, an IEEE IPFA Best Paper Award, and the 2011 IEEE EDS Paul Rappaport Award. He has served or is serving at various functions at the IEDM, IRPS, SISC, INFOS, and WoDiM conferences. He is currently serving on the IEEE T. Electron Dev. Editorial Board.

ABSTRACT:Design and fabrication of devices with record performance is meaningless if this performance cannot be maintained for the entire lifetime of the application. Consequently, the degradation of FET device parameters during operation has to be evaluated for successful qualification of each technology. Accelerated reliability testing can be correctly projected to operating conditions only if the underlying degradation mechanisms are well understood. This understanding has to be extended to new device architectures and materials currently being introduced or considered.

This tutorial will attempt to build a fundamental physical understanding of two FEOL crucial reliability mechanisms, Time-Dependent Dielectric Breakdown (TDDB) and Bias Temperature instability (BTI). This in turn will allow describing the acceleration and scaling properties of these mechanisms, as well as explaining their impact on various device parameters. The reliability projection process for both mechanisms will be illustrated. It will be further shown how the reliability margins are constantly decreasing due to the continuous downscaling of device dimensions without the corresponding supply voltage reduction. When technological solutions start to be inadequate, it will be shown that some reprieve can be achieved by considering the particular function of each device in the surrounding circuit.

BIO: Research Director and Head of HW-SW Integration programs at CEA-LETI, received the Engineer degree from the University of Tunis in 1980 and the D.E.A., "Docteur Ingénieur", and the "Docteur d'Etat" degrees from the University of Grenoble in 1981, 1983, and 1989 respectively, all in computer sciences. In 1986, he held a full research position with the CNRS (Centre National de la Recherche Scientifique). From April 1990 to March 1991, he was a Member of the Scientific Staff at Nortel in Canada, working on linking system design tools and hardware design environments. He served as General Chair for DATE 2001 and as general chair of ESWEEK2012. He also served as a general chair or program chair of several international Workshops and symposia. He cofounded MPSoC (Multiprocessor SoC), the pluridisciplinary forum. He published 200 papers in International Conferences and Journals and 9 books. He received the Best Paper Award at the 1994 ED&TC for his work on Hardware/Software Co-simulation. He was Secretary of the European Design Automation Association (EDAA) from January 2000 to December 2004. He has been European Representative for Design Automation Conference in USA 2002-2006. He joined CEA-LETI in 2007.

ABSTRACT: IC markets are dominated by computing MPSoC. combining cores, Logic, Memory and I/O. The key challenge for future high-end computing MPSoC wil be energy efficiency. This in addition to all the usual stringent contraints: Yield/Cost, Static power, data transfer and I/O, Heterogeneous Integration. Several emerging semiconductor technologies will allow orders of magnitude improvement in energy efficiency and to mitigate the classical design constraints. 3D is Happening To improve poser consumption and yield and cost. It will also allow shortening distances and increases bandwidth in a single chip. To improve energy efficiency of off-chip I/O, Si-Photonics will be soon required for chip to chip on board and later on silicon Interposer (2.5D). eNVM will enable reducing static power consumption. Finally Heterogeneous Integration will be required to increase miniaturization. The implication of this evolution will be disruptive for the whole semiconductor and electronic eco-system. This presentation will analyze the evolution of the semiconductor Market and show the required semiconductor innovations towards gaining orders of magnitude in energy efficiency when designing high performances computing MPSoC.

BIO: Edgar Sánchez-Sinencio, TI J. Kilby Chair Professor, Texas A&M University (F'92, LF'09). He was born in Mexico City, Mexico. He received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, the M.S.E.E. degree from Stanford University, Stanford, CA, and the Ph.D. degree from the University of Illinois at Champaign-Urbana, in 1966, 1970, and 1973, respectively. He has graduated 48 M.Sc. and 39 Ph.D. students, among them 8 Egyptian Ph. Ds. He is a co-author of six books on different topics, such as RF circuits, low-voltage low-power analog circuits, and neural networks. He is currently the TI J. Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. His current interests are in the area of power management, ultra-low power analog circuits, data converters and medical electronics circuit design. He is a former Editor-in-Chief of IEEE Transactions on Circuits and Systems II and a former IEEE CAS Vice President–Publications. In November 1995 he was awarded a Honoris Causa Doctorate by the National Institute for Astrophysics, Optics and Electronics, Mexico. This degree was the first honorary degree awarded for microelectronic circuit-design contributions. He is a co-recipient of the 1995 Guillemin-Cauer Award for his work on cellular networks. He received the Texas Senate Proclamation # 373 for Outstanding Accomplishments in 1996. He was also the co-recipient of the 1997 Darlington Award for his work on high-frequency filters. He received the IEEE Circuits and Systems Society Golden Jubilee Medal in 1999. He is the recipient of the prestigious IEEE Circuits and Systems Society 2008 Technical Achievement Award. He was the IEEE Circuits and Systems Society's Representative to the IEEE Solid-State Circuits Society during 2000–2002. He was a member of the IEEE Solid-State Circuits Society Fellow Award Committee from 2002 to 2004. He is currently (2012-2013) a Distinguished Lecturer of the IEEE Circuit and Systems Society.

ABSTRACT: This review analyzes and classifies previously published CMOS low noise amplifier (LNA) linearization techniques: a) feedback; b) harmonic termination; c) optimum biasing; d) feedforward; e) derivative superposition (DS); f) IM2 injection; g) noise/distortion cancellation; and h) post-distortion. This tutorial also addresses broadband-LNA-linearization issues for emerging reconfigurable multiband/multistandard and wideband transceivers. Furthermore, we highlight the impact of CMOS technology scaling on linearity and outline how to design a linear LNA in a deep submicrometer process.

BIO: Cliff Sze is a research staff member at the IBM Austin Research Laboratory, Austin, Texas, where he focuses on integrated placement, routing and timing optimization for ASIC and microprocessor designs. Cliff has contributed to several IBM ASIC designs, as well as POWER 6, POWER 7, Xbox 360 and the Sony/Toshiba/IBM CELL processors for PlayStation consoles. He received several IBM technical/invention awards, filed more than 25 patents applications and was granted 10+ patents worldwide. His research interests include design and analysis of algorithms, computer-aided design technique for very large scale integration, physical design, and performance-driven interconnect synthesis. He received his B.Eng. and M.Phil. degrees from the Department of Computer Science and Engineering, the Chinese University of Hong Kong and his Ph.D. degree in computer engineering at the Department of Electrical Engineering, Texas A&M University.

Dr. Cliff Sze has been actively serving the academic/research community, for example, on the program committees for ICCAD, ASPDAC, ISPD, SLIP, SOCC, and as a reviewer for top journals such as IEEE TCAD, IEEE TVLSI as well as IEEE TCAS. He also has served as a mentor for several SRC projects, as the program chair of International Symposium on Physical Design 2013, as the contest chair of the global routing and clock network synthesis contests in ISPD (2008-2010), as the Computer-Aided Network Design track chair for ISCAS 2011 and 2012, and as the Silicon Design (Back-End) track chair of the 2013 DAC DesignerTrack. Dr. Sze was the recipient of the ACM/SIGDA Technical Leadership Award and the IEEE/ACM Design Automation Conference Graduate Scholarships. In order to promote EDA research and industry-academia collaboration, he has given more than 15 invited talks to the top universities worldwide.

ABSTRACT: It is well-known that scaling of VLSI feature size has shifted the EDA research focus from logic synthesis to physical design. In the last decade, some researchers claimed that logic synthesis is dead and (placement centric) physical synthesis has gained great popularity. It is obvious that wire delay dominates the total path delay, and therefore, placement becomes the most critical factor to timing yield. However, some EDA researchers may not observe the evolving real challenge for timing closure in the latest technology nodes -- the routability problem.

When hierarchical methodology and SOC designs becomes the mainstream, placement blockages are pervasive in the layout and thick wires are inevitable for global (or even local) interconnects. This greatly reduces the number of available wiring tracks. Unfortunately, scaling led to an ever-increasing demand on routing resource. This combination became a perfect storm for routability, which results in wire detours and becomes a brick wall for timing closure. In this talk, I will detail the routability problem in the industry and explain the latest research in routing, and routability-driven timing-driven flow.

BIO: Luciano Ost is Associate Professor at the University of Montpellier II (UM2) and member of Adaptive Computing Group at LIRMM, which is a cross-faculty research entity of the UM2 and the National Center for Scientific Research (CNRS), France. Ost worked one year as invited research at the Microelectronic Systems Institute of the Technische Universitaet Darmstadt (from 2007 to 2008). Further, Ost got his PhD degree in Computer Science from PUCRS, Brazil in 2010. From 2004 to 2006 he worked as Research Assistant in this same University. His main research interests include heterogeneous and adaptive multiprocessor architectures and embedded system modelling and simulation.

ABSTRACT: The growing concerns of power efficiency, silicon reliability and performance scalability motivate research in the area of adaptive embedded systems. Embedded applications cause time-varying workloads on the underlying systems, such as the scenarios when the system interacts with complex deployment environments or user-driven requests. To cope with such scenarios, the deployment of new techniques to achieve runtime system adaptability is mandatory to meet performance criteria, such as application performance or power consumption. This tutorial course describes adaptive embedded system concepts, gives an overview of existing techniques, presents few approaches, and gives examples on practical cases developed in the ADAC group.

BIO: Received his Master's degree in Electronics Engineering and Microelectronics from the ENSEIRB (France) joint with the University of Bordeaux (France) in 2006. In 2010, he received his PhD degree in Microtechnology from the University of Neuchatel (Switzerland) joint with the PhD degree in Electronics from the University of Bordeaux. Currently, he is a post-doctoral researcher at UFRGS (Universidade Federal do Rio Grande do Sul) at Brazil. His research interest is focused in applied electronics for biomedical applications, including Smart Neural Prosthesis, Analog/Mixed/Digital Integrated Circuits, Bioelectronic Closed-loop systems, and Design-for-dependability of heterogeneous systems.

ABSTRACT: In this tutorial we will present recent advances in a particular field of Bioelectronics, the development of Neuroprotheses. Neural prostheses are devices that substitute or improve a motor, sensory or cognitive function. This field has started with the study of "animal electricity" in the 18th century and is emerging nowadays with the advances in Biomedicine, Materials and, of course, Micro- Nanoelectronics. We will cover successful and futuristic examples. The successful ones include Cochlear Implants for hearing rehabilitation and Deep Brain Stimulation for the symptomatic treatment of Parkinson Disease. Futuristic devices includes Cognitive Prostheses which could offer remedies for the cognitive and memory loss accompanying Alzheimer's disease or the speech and language deficits resulting from stroke.