Algorithm
and VLSI Design for a High Quality Motion Estimation Focused on High
Definition Videos
Gustavo Sanchez, Marcelo
Porto, Luciano Agostini
A
Memory Aware VLSI Architecture for the Complete Intra-Frame
Prediction of the Emerging HEVC Standard
Daniel Paomino, Felipe
Sampaio, Luciano Agostini, Sergio Bampi, Altamiro Susin
Parallel
Motion Estimation Implementation for Different Block Matching
Algorithms onto GPGPU
Eduarda Monteiro, Marilena
Maule, Felipe Sampaio, Cláudio Diniz, Bruno Zatt, Sergio Bampi
Reconfigurable
Architecture for 1-D Discrete Cosine Transform of the HEVC Emerging
Video Encoding Standard
Hecktheuer, Bruno;
Conceição, Ruhan; Wrege, Gustavo; Souza, José Cláudio; Jeske,
Ricardo; Agostini, Luciano; Mattos, Júlio C. B.
Evaluating
the Impact of Carry-Ripple and Carry-Lookahead Adders in Pel
Decimation VLSI Implementations
Ismael Seidel, Bruno
George de Moraes, José Luís A. Güntzel
Low
complexity heuristic for the inter-prediction PU decision step on
HEVC encoders
Mateus Grellert, Felipe
Sampaio, Luciano Agostini, Julio C. B. Mattos
A
New Motion Estimation Algorithm for High Definition Videos and its
Hardware Design
Pargles Dall'Oglio,
Cássio Cristani, Marcelo Porto, Luciano Agostini
A
New Motion Estimation Algorithm of Low Computational Cost and
Focusing on Full HD Videos
Cássio Cristani, Pargles
Dall'Oglio, Marcelo Porto, Luciano Agostini
RFCAVLC8t:
a Reference Frame Compression Algorithm for Video Coding Systems
Dieison Silveira, Mateus
Grellert, Luciano Agostini
A
Dedicated Hardware Solution for the HEVC Interpolation Unit
Vladimir Afonso, Marcel
Moscarelli Corrêa, Luciano Volcan Agostini, Denis Teixeira Franco
Architectural
Design for the Adaptive Loop Filter of the Emerging High Efficiency
Video Coding Standard
Fabiane Rediess, Cássio
Cristani, Pargles Dall'Oglio, Marcelo Porto, Luciano Agostini
Simulation-Based
Evolutionary Heuristic to Sizing Analog Integrated Circuits
Lucas Compassi Severo,
Alessandro Girardi
Automatic
Design of Micropower Carbon Nanotube Operational Transconductance
Amplifiers
Tanísia Possani, Lucas
Compassi Severo, Alessandro Girardi
Structural
and luminescence properties of Ge nanocrystals before and after an
ion irradiation process
F. Nornberg, F. L.
Bregolin, U. S. Sias
FPGA
Implementation of Neural Network for EEG Signal Processing
Thiago Pontes, Rodrigo
Braga, Carla Becker, Eduardo Costa, Sérgio Almeida
Combination
of Strategies to Improve the Yield in Networks-on-Chip Links
Anelise Kologeski,
Caroline Concatto, Fernanda Lima Kastensmidt, Luigi Carro
Node
localization in Wireless Sensor Networks Using Artificial Neural
Networks and Optimization Based on Simulated Annealing Algorithm
Stephan H. Chagas,
Leonardo L. de Oliveira, João Baptista S. Martins
A
Progressive Approach for Fault Tolerance Improvement in Digital IPs
Tian BAN, Lirida NAVINER
Mobility
Support Enhancements for a Wireless Sensor Network Framework
Raphael A. Camponogara
Viera, Luana Palma, Leonardo Londero de Oliveira, João Baptista
Martins
ARMAX
Model of Elastic Nuclei for Rotors MEMS
Manuel Reimbold, Airam
Sausen, Luiz Rasia, Andre Bedendo, Cicero Moreira
An
analysis of power and performance of applications for mobile devices
with Android OS
Andrws Vieira, Daniel
Debastiani, Luciano Agostini, Felipe Marques, Júlio Mattos
Modeling
Android applications using UML
Abilio G. Parada, Thiago
A. Alves, Lisane Brisolara
Embedded
Software Modeling using UML2: A Case Study
Eliane Siegert, Milena
Marques, Lisane Brisolara
Comparing
Two Asynchronous IC Design Flows
Matheus Moreira, Ney
Calazans
An
8 point DCT-II multiplierless architecture based on CMM
Marciano Prates Salbego,
Sidinei Ghissoni, João Guilherme Nizer Rahmeier
Low
Power 3-2 and 4-2 Adder Compressors Implemented Using ASTRAN
Jorge Tonfat, Ricardo Reis
Demonstrating
Grover's Quantum Search Algorithm
Marina Miranda, Calebe
Conceição, Ricardo Reis
Challenges
for Optimization of Transistors Array-based Via-Configurable Regular
Layout
V. Dal Bem, A. I. Reis, R.
P. Ribas
A
Low-Power High Throughput Configurable FFT/IFFT Processor for WLAN
and WiMax Protocols
Renan Netto, Pedro Michel,
José Luís A. Güntzel
2-Coefficient
Fixed Point Hardwired Adaptive Filtering Based on LMS Algorithm
Maique Garcia, Gustavo
Seibel, Eduardo da Costa, Sérgio Almeida
Reducing
Area and Power in FFT Architectures Using Twiddle Factor
Decomposition Approach
Sidinei Ghissoni, Eduardo
Costa, Ricardo Reis
Design
of 16nm SRAM Architecture
Iuri A. C. Gomes, Cristina
Meinhardt, Paulo F. Butzen
Full
Adders Architectures Evaluation for 32nm Technology
Augusto Silva, Ingrid
Machado, Cristina Meinhardt, Paulo F. Butzen
Evaluating
the Efficacy of Low Power Process to Design Low Power Circuits
Cícero S. Nunes, Augusto
N. Silva, Iuri A. C. Gomes, Cristina Meinhardth, Paulo F. Butzen
VLSI
Design for a Memory Efficient Motion and Disparity Estimation of the
Multiview Video Coding
Felipe Sampaio, Bruno
Zatt, Sergio Bampi, Luciano Agostini
Matrices
Manipulation for the Implementation of a Hardwired Affine Projections
Algorithm for Acoustic Echo Cancelling
Aminadabe Soares , Sérgio
Almeida, Eduardo Costa
Building
a Bitcoin Miner on an FPGA
Samuel Oliveira, Filipe
Soares, Guilherme Flach, Marcelo Johann, Ricardo Reis
Logic
Gates Design for Aging Enhancement
Paulo F. Butzen, Vinícius
Dal Bem, André I. Reis, Renato P. Ribas
A
Reconfigurable Digital Decimation Filter Design for a Cascade 2-2
Sigma-Delta Analog-to-Digital Converter
Crístian Müller, Paulo
César C. de Aguirre, Cesar A. Prior and João B. S. Martins
Transistor
Sizing and Gate Sizing Using Geometric Programming Considering Delay
Minimization
Gracieli Posser, Guilherme
Flach, Gustavo Wilke, Ricardo Reis
Reliability
Estimation Methods: Trade-offs Between Complexity and Accuracy
Samuel N. Pagliarini,
Denis T. Franco, Lirida A. de B. Naviner and Jean-François Naviner
Negotiation-Based
Global Routing for VLSI Circuits
Tiago J. Reimann, Ricardo
A. L. Reis
Simulation
of SET Faults in a Voltage Controlled Oscillator
Walter Calienes Bartra,
Ricardo Reis
Introducing
Read-Polarity-Once Functions
Vinicius Callegaro, Renato
P. Ribas, André I. Reis
Applications
of Functional Composition
Mayler G. A. Martins,
Renato Perez Ribas, André Inácio Reis
An
Introduction of Geometric Programming Using Gate Sizing
Jozeanne Belomo, Gracieli
Posser, Guilherme Flach, Ricardo Reis
Introducing
K-cuts and KL-cuts in Circuit Re-Mapping
Lucas Machado, Osvaldo
Martinello, Renato Perez Ribas, André Reis
A
graph-based approach for Boolean matching
Anderson Santos da Silva,
Vinicius Callegaro, Renato Ribas, André Reis
NSP
Kernel Finder - A Methodology to Find Non-Series-Parallel
Arrangements
Vinicius Neves Possani,
Vinicius Callegaro, Andre Inácio Reis, Renato Peres Ribas, Felipe
Souza Marques, Leomar Soares da Rosa Jr.
An
Effective Method for Generating Boolean Signatures
Renato S. de Souza,
Vinícius N. Possani, Julio S. Domingues Jr, Felipe S. Marques,
Leomar S. da Rosa Jr.
Exploration
of Technology Mapping Flow for QCA Designs
Julio S. Domingues Jr,
Douglas Detoni, Leomar S. da Rosa Jr, Felipe Marques
Heuristic-Based
Algorithms for the Ordering of Gray Encoded Twiddle Factors of FFT
Architectures
Angelo G. da Luz, Eduardo
A.C da Costa, Sidinei Ghissoni
An
Educational Tool For Teaching Simulated Annealing And Placement
Tania Mara Ferla,
Guilherme Flach, Ricardo Reis
A
Brief Analysis of Using Transistor Networks
Gerson Scartezzini,
Ricardo Reis
Technology
Mapping for QCA Device
Stèphano Gonçalves,
Mayler Martins, Melissa Colvara, André Reis, Renato Ribas, Leomar
Rosa Jr., Felipe Marques
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