Rethinking Memory System Design for Data-Intensive Computing

ONUR MUTLU
Carnegie Mellon University, USA

October 22nd, Thursday, 9:00

Abstract: The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck. At the same time, DRAM and flash technologies are experiencing difficult technology scaling challenges that make the maintenance and enhancement of their capacity, energy- efficiency, and reliability significantly more costly with conventional techniques. In this talk, we examine some promising research and design directions to overcome challenges posed by memory scaling. Specifically, we discuss three key solution directions: 1) enabling new memory architectures, functions, interfaces, and better integration of the memory and the rest of the system, 2) designing a memory system that intelligently employs multiple memory technologies and coordinates memory and storage management using non-volatile memory technologies, 3) providing predictable performance and QoS to applications sharing the memory/storage system. If time permits, we might also briefly touch upon our ongoing related work in combating scaling challenges of NAND flash memory.

An accompanying paper can be found here:

Short Bio: Onur Mutlu is the Strecker Early Career Professor at Carnegie Mellon University. His broader research interests are in computer architecture and systems, especially in the interactions between languages, system software, compilers, and microarchitecture, with a major current focus on memory systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. Prior to Carnegie Mellon, he worked at Microsoft Research, Intel Corporation, and Advanced Micro Devices. He was a recipient of the IEEE Computer Society Young Computer Architect Award, Intel Early Career Faculty Award, faculty partnership awards from various companies, a number of best paper recognitions at various top computer systems venues, and a number of "computer architecture top pick" paper selections by the IEEE Micro magazine. For more information, please see his webpage at Link

5G transceiver: RFIC Design by Mathematics

Francois Rivet
Université de Bordeaux

October 22nd, Thursday, 11:00

Abstract: Wireless system designers have been facing the continuously increasing demand for high data rates and mobility required by new wireless applications and therefore have started research on new generation of wireless systems that are expected to be deployed beyond 2020. 5G wireless networks will support 1,000-fold gain in capacity, connections for at least 100 billion devices, and a 10 Gbps individual user experience capable of extremely low latency and response times. Deployment of these networks will emerge between 2020 and 2030. It is clearly observed that new solutions are required. The focus of this presentation will be on the RFIC Design by Mathematics of 5G transceiver, exploring novel approaches along with a thorough discussion of advanced techniques for these receivers and transmitters towards a revolution in RF integrated circuits and systems design. Design by Mathematics is a disruptive of way of thinking in RFIC design. It uses mathematical properties for signal processing in RF signal conditioning, from baseband to RF Front-End. These mathematical properties are integrated in silicon to display the best trade-off in terms of power consumption, dynamic range, wide bandwidth, frequency agility and modulation schemes. The work is brought at a high system level and enables to relax constraints compared to traditional RF architectures.

Short Bio: Dr. Francois Rivet received the Master degree in 2005 from Electrical Engineering Graduate School of BORDEAUX in Southwest of France (ENSEIRB) and the PhD degree in 2009 from the University of BORDEAUX, France. He joined the French Research Agency (CNRS) in 2005 as a PhD student. His PhD activities took place at IMS, the microelectronics laboratory of the University of BORDEAUX. His research is focused on the design of RFICs with a dedicated methodology (“Design by Mathematics”). He is a member of the STMicroelectronics-IMS joint research laboratory. Dr. Rivet has publications in top ranked journals, international conferences, national conferences and holds 9 patents. He received the Best Paper Award at Software Defined Radio Forum in 2008 at Washington DC, USA. He is member of several Technical Program Committees (RFIC, MWSCAS, SBCCI, …). Since June 2010, he is tenured as Associate Professor at IMS Lab and Bordeaux Institute of Technology. In 2014, he founded the “Circuits and Systems” team at IMS Lab.

Fast Prototyping: A Must in Current Electronic System Design Methodology

Victor Grimblatt
Synopsys

October 22nd, Thursday, 14:00

Abstract: The role of electronics in our life has changed dramatically over the last decade. This change started almost 10 years ago with the smartphone introduction when applications moved from desktop to mobile devices. A similar electronic revolution is happening in the automotive industry. Fuel consumption and emissions are driving new hybrid and electric vehicles; the market is also interested on safety and is pushing for new concepts for automotive drive assistance systems (ADAS). Self-driving cars are becoming a reality. We are seeing comparable boosts of electronics in other markets such as consumer and industrial applications. Finally the emergence of Internet of Things (IoT) will take the involvement of electronics in our lives to a whole new level. All those devices are processing information and communicating with the surrounding environment. The advancement in silicon complexity as well as the software running on those devices make it possible. The increase in the amount and complexity of the software content is putting more pressure on the entire supply chain to meet time to market, differentiation, and quality expectations. Companies have been adapting their processes to provide more functionality through software and improve the impact of software on the performance and power consumption. At the same time they are reducing the software schedule dependency from hardware availability through prototyping. During the presentation will review the prototyping methodologies and how the dependency on hardware is mitigated. We will also review how prototyping helps on early architecture exploration and selection, software development, hardware-software integration, and system validation.

Short Bio: Victor Grimblatt was born in Viña del Mar, Chile. He has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is currently R&D Group Director and General Manager of Synopsys Chile, leader in Electronic Design Automation (EDA). He opened the Synopsys Chile R&D Center in 2006. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore he is often consulted for new technological business development. Before joining Synopsys he worked for different Chilean and multinational companies, such as Motorola Semiconductors, Honeywell Bull, VLSI technology Inc., and Compass Design Automation Inc. He started to work in EDA in 1988 in VLSI Technology Inc. where he developed synthesis tools being one of the pioneers of this new technology. He also worked in embedded systems development in Motorola semiconductors. In 1990 he was invited by professor McCluskey to present his work in Logic Synthesis at the CRC – Stanford University. He has published several papers in EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, and Embedded Systems. From 2006 to 2008 he was member of the “Chilean Offshoring Committee” organized by the Minister of Economy of Chile. In 2010 he was awarded as “Innovator of the Year in Services Export”. In 2012 he was nominated to best engineer of Chile. He is also member of several Technical Program Committees on Circuit Design and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. Victor Grimblatt is from 2002 professor of Electronics and IC Design in Universidad de Chile and Universidad de los Andes.

New Developments in state-of-the-art Video Coding

Luis Alberto da Silva Cruz
Universidade de Coimbra, Portugal

October 22nd, Thursday, 16:20

Abstract: In 2013 the current state-of-the-art video coder, H.265/HEVC version 1, reached the final standard status. Although H.265/HEVC provided enormous coding efficiency gains in comparison to its predecessor, H.264/AVC, its development did not stop, and after incorporation of several new tools to handle, for e.g. 3D video a new version 2 is now available. The emergence of new signal formats like HDR video, plenoptic video and point-cloud 3D video poses new challenges to video coding technology. To address these challenges explorations on improvements to HEVC/H.265 have already begun, with provisional impressive results. This talk will cover briefly the history of video coding technology, mostly since MPEG-2, to then describe the latest generation codec (HEVC) in some detail. After that the speaker will introduce new video content representation formats and discuss the implication of their adoption to the video coding technology. The talk will end with a sum-up of recent research and development results in the field.

Short Bio: Luis A. da Silva Cruz (M’11) received the Licenciado and M.Sc. degrees in Electrical Engineering from the University of Coimbra, Portugal, in 1989 and 1993, a M.Sc. degree in Mathematics and a Ph.D. degree in Electrical Computer and Systems Engineering from Rensselaer Polytechnic Institute (RPI), Troy, NY, US in 1997 and 2000 respectively. He has been with the Department of Electrical and Computer Engineering of the University of Coimbra in Portugal since 1990 first as a Teaching Assistant and as an Assistant Professor since 2000. He is a researcher of the Institute for Telecommunications, Portugal, where he he has been working on video processing and coding, mainly video codec technology, wireless communications and medical image and video processing for automatic diagnostic applications.

Accelerating Bioinformatics Algorithms with Reconfigurable Devices

Ricardo Jacobi
Universidade de Brasilia

October 23nd, Friday, 9:00

Abstract: High Performance Computing (HPC) can be achieved through a variety of technologies. From the classic supercomputers to today’s heterogeneous platforms combining high performance processors, GPUs, many core systems and FPGAs, the evolution of HPC is related to the state of art in semiconductor technology and architectures. The use of FPGA to accelerate algorithms is gaining momentum due to the large amount of parallelism it provides and the power reduction obtained by migrating algorithms to dedicated hardware. Bioinformatics is a research field dedicated to the processing of biological data. Sequence comparison and sequence alignment are two basic operations which aims to find the similarity between two genomic sequences and find the alignment that produces the best matching between them. Since sequences can be huge, HPC is needed to speed up the process. Some dedicated architectures to tackle these problems are presented, based on wavefront processing vectors.

Short Bio: Received a PhD in Applied Science - Université Catholique de Louvain in 1993. He was professor of UFRGS Informatic Institute from 1989 to 1998, when joined UnB. He is currently associate professor of the Computer Science Department at the University of Brasilia. He was Director of the Institute of Exact Sciences at UNB from 2004 to 2007 and Vice-Director of the Campus UnB Gama from 2008 to 2012. His research areas are reconfigurable arquitectures and applications, hardware and software codesign and dedicated architectures for high performance computing.

IBM Design Closure Flow for High Performance Microprocessors

Gi-Joon Nam
IBM T. J. Watson Research Center, USA

October 23nd, Friday, 11:00

Abstract: As VLSI technology scales down further to meet the demands of Moore’s law, interconnect delays become the dominant factor in timing optimization. Coupled with conflicting optimization objectives such as delay, area, routability and design for manufacturability, the design closure problem of complex VLSI designs becomes almost intractable. This presentation will introduce the IBM design closure methodology and address the engineering concepts that shape a modern layout synthesis flow. IBM design closure methodology has demonstrated significant success for high performance microprocessor designs in IBM flagship products such as P/Z servers. Then, I will conclude the talk that this still is an exciting time to be a computer & electrical engineers with tremendous opportunities laying ahead in VLSI and architecture areas.

Short Bio: Gi-Joon Nam is a research staff member and manager at the IBM T. J. Watson Research Center. He currently manages the Physical Design department. His group is conducting research on various design automation techniques for high performance computing IBM products such as IBM’s P/Z microprocessors and server chips. Prior to this, he has managed the Optimized Analytics System department at the IBM Austin Research Lab working on the workload optimized systems for big data applications. Gi-Joon has been involved with leading-edge high performance VLSI designs for 15+ years, starting from 130 nm technology nodes to sub-20 nm technologies.

IC Physical Implementation Challenges in sub-20nm CMOS Nodes

Andrew B. Kahng
UC San Diego, USA

October 23nd, Friday, 14:00

Abstract: IC physical implementation is where “rubber meets the road” for power, performance, area and cost in leading-edge CMOS nodes. This talk will highlight new challenges, as well as promising optimization levers, for physical implementation in sub-20nm process technologies. The list of challenges includes (i) BEOL resistivity and variability; (ii) greater discreteness in sizing due to fewer fins and threshold voltages; (iii) a “race to the end of the roadmap” which causes too-hasty design enablement; (iv) a growing loss of model-hardware correlation; and (v) the breakdown of old algorithms and methodologies in the face of today’s explosion of signoff modes and corners. Available levers to meet these challenges include (i) on-chip adaptivity; (ii) holistic margin recovery; (iii) improved design signoff criteria; (iv) “closing the loop” in the performance analyses that drive circuit optimizations; and (v) 3-dimensional integration.

Short Bio: Andrew B. Kahng is Professor of CSE and ECE at UC San Diego, where he holds the endowed chair in High-Performance Computing. He has served as visiting scientist at Cadence (1995-1997) and as founder, chairman and CTO at Blaze DFM (2004-2006). He is the coauthor of 3 books and over 400 journal and conference papers, holds 30 issued U.S. patents, and is a fellow of ACM and IEEE. He has served as general chair of DAC, ISQED, ISPD and other conferences. He has also been international chair/co-chair of the Design technology working group, and recently of the System Integration focus team, in the ITRS since 2000. His research interests include IC physical design and performance analysis, the IC design-manufacturing interface, combinatorial algorithms and optimization, and the roadmapping of systems and technology.

Timing-Driven Placement

José Luís Güntzel
UFSC, Brazil

October 23nd, Friday, 16:20

Abstract: Timing closure is currently one of the most challenging tasks in the design of VLSI circuits. Several techniques are iteratively applied along the physical design flow to meet the timing constraints such as gate sizing, buffer insertion, timing-driven routing and timing-driven placement. Among these techniques, timing-driven placement (TDP) is probably the one with highest timing optimization potential since it finds new legal locations for standard cells based on quite accurate circuit delay information which generally results in shorter interconnect delays. This talk reviews some of the most important TDP techniques found in the literature, pointing out their main features. Although the quality of global placement has significantly advanced in the last years, there is still a lack of efficient techniques to address the TDP problem. Therefore, this talk also presents a Lagrangian Relaxation formulation for TDP that compresses both late and early slack histograms while preserving the placement quality.

Short Bio:José Luís Güntzel received the Electrical Engineering degree from the Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1990. He received both the M.Sc. and the Ph.D. degrees in Computer Science also from the Federal University of Rio Grande do Sul (UFRGS) in 1993 and 2000, respectively. Since 2007, Dr. Güntzel is an Associate Professor at the Department of Informatics and Statistics of the Federal University of Santa Catarina (Florianopolis, Brazil). His research interests include physical design automation, timign analysis, memory optimization for low-power embedded computing systems and energy-efficient VLSI architectures for video compression. Dr. Güntzel is a member of the IEEE/IEEE-CAS, the Brazilian Microelectronics Society and the Brazilian Computer Society.