| Preliminary Program |
| IBERCHIP and LASCAS at a Glance |
| Tuesday: February 23th | Wednesday: February 24th | Thursday: February 25th | Friday: February 26th | ||||||||||||||
8:30-9:00 |
Opening | ||||||||||||||||
9:00-10:00 |
Keynote Speaker - Maciej Orgozalek | 9:00-10:00 | Keynote Speaker - Giovanni De Micheli | Invited Speaker - Paulo Diniz | 9:00-10:00 | Invited Speaker - Massimo Alioto | |||||||||||
10:00-10:30 |
Invited Speaker: Patrícia Lustoza de Souza | 10:00-10:30 | Coffee-break | Coffee-break | 10:00-10:30 | Coffee-break | |||||||||||
10:30-11:00 |
Invited Speaker: Roberto Mendonça Faria | 10:30-12:10 | Session 1: LASCAS | Session 2: LASCAS | Session 7: Iberchip | Session 8: Iberchip |
Session 5: LASCAS | Session 6: LASCAS | Session 11: Iberchip | Session 12: Iberchip | 10:30-12:10 | Session 8: LASCAS |
Session 9: LASCAS | ||||
11:00-11:20 |
Coffee Break | ||||||||||||||||
11:20-12:10 |
Round Table Namitec | ||||||||||||||||
| 12:10-14:00 | Lunch | Lunch | 12:10-14:00 | Lunch | |||||||||||||
12:40-14:00 |
Lunch | ||||||||||||||||
14:00-15:15 |
Session 1: Iberchip | Session 2: Iberchip | Session 3: Iberchip | Session Namitec | 14:00-15:15 | Embedded Tutorial 1 | Embedded Tutorial 2 | 14:00-15:15 | Embedded Tutorial 3 | ||||||||
| 15:15-16:15 | Poster Session and Coffee-break | Poster Session and Coffee-break | 15:15-15:45 | Coffee-break | |||||||||||||
15:40-16:30 |
Posters and Coffee Break | 15:45-17:55 | Session 10: LASCAS |
Session 11: LASCAS | |||||||||||||
| 16:15-17:55 | Session 3: LASCAS | Session 4: LASCAS | Session 9: Iberchip |
Session 10: Iberchip | Session 7: LASCAS | Special Session (Biomedical Circuits and Systems) | Session 13: Iberchip | Session 14: Iberchip | |||||||||
16:30-18:10
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Session 4: Iberchip | Session 5: Iberchip | Session 6: Iberchip | Session Namitec | |||||||||||||
18:10-19:10 |
Special Session dedicated to Tere Oses | ||||||||||||||||
19:10 |
18:20 | Visit to Itaipu Dam | 17:55 | Closing | |||||||||||||
20:30 |
20:30 | Conference Dinner | |||||||||||||||
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Iberchip Program
Tuesday: February 23th |
|
| 9:00 to 10:00 | Can Fractal Microelectronics Solve Nano-Tera Problems? Keynote Speaker: Maciej Orgozalek |
| 10:00 to 10:30 | Fabricação de nanoestruturas semicondutoras auto-organizadas e sua aplicação em dispositivo Invited Speaker: Patrícia Lustoza de Souza |
| 10:30 to 11:00 | Eletrônica orgânica. Invited Speaker:Roberto Mendonça Faria |
| 14:00 to 15:40 |
Session i1 - ARITHMETIC CIRCUITS Efficient Pipelined Radix-2m Wallace Multiplier João Altermann, Leandro Zafalon and Eduardo da Costa Somadores Tolerantes a Falhas Usando BSD e Codificação 1 de 3 Helen Franck, José Güntzel, Gustavo Wilke and Ricardo Reis Diseño hardware de un multiplicador de matriz dispersa - vector usando la representación CSR Jorge Eduardo Guerrero Ramirez and Jaime Velasco-Medina Aritmética RNS y caos aplicados para generar números pseudoaleatorios en dispositivos programables Carlos Arturo Gayoso Síntesis Física del Módulo de División de N bits con Segmentación v1.10 Walter Calienes Bartra, Manuel Monge Osorio, Carlos Silva Cárdenas and Ricardo Reis Session i2 - CAD TOOLS 1 Migração de Circuitos VLSI 2D para 3D Dirigida a Redução de Interconexões Verticais (TSV) Sandro Sawicki, Marcelo Johan and Ricardo Reis A 3D Symbolic Routing Viewer of Digital Integrated Circuits Erico Nunes and Reginaldo Tavares On Methods for Extraction of Typical Linear Driver Resistance Tiago J. Reimann, Glauco B. V. Santos and Ricardo A. da Luz Reis Estudo do impacto da variabilidade em um conjunto de blocos básicos para composição de leiautes regulares Cristina Meinhardt, Jerson Paulo Guex and Ricardo Reis Estimador de Potência e Atraso em Standard-Cells Utilizando Redes Neurais Artificiais Daniel Guimarães Jr, Ulisses Correa, Luigi Carro and Ricardo Reis Session i3 - ANALOG DESIGN 1 VGA lineales en dB con corriente de control exponencial PWL David Moro-Frias, Ma. Teresa Sanz-Pascual, Carlos Aristoteles De la Cruz-Blas and Arturo Sarmiento-Reyes Design procedure of a linearized OTA based on transconductance, harmonic distortion and mismatch specification Julio Saldaña-Pumarica and Emilio Del-Moral-Hernandez Diseño de un OTA de baja transconductancia para el acondicionamiento de señales ECG Mikel Ormazabal Módulo multi-função para interface entre fotodetectores e circuitos analógicos condicionadores de sinal Lester de Abreu Faria, Fabio Durante Pereira Alves and Newton Gomes |
| 15:40 to 16:30 | POSTER SECTION 1 IP-Core para Compressão Sem Perdas de Sinais Biológicos (DEMO) Daniel Soares e Marques, Yuri Gonzaga Gonçalves da Costa, Bruno Maia de Morais, João Janduy Brasileiro Primo, Igor Gadelha Pereira, Lucas Lucena Gambarra, José Antônio Gomes de Lima, Antônio Carlos Cavalcanti and Leonardo Vidal Batista Implementación en Hardware de Algoritmos Para Efectos de Audio Usando FPGAs Pedro Pablo Lievano-Torres, John Michael Espinosa-Duran and Jaime Velasco-Medina Reconocimiento de Voz Aplicando Mapas Auto-Organizativos Matias Namiot, Laura Lanzarini, José A. Rapallini and Antonio A Quijano Uso de DSP para Análisis de Ruidos en Señales de Baja Frecuencia Julián Marchueta, José A. Rapallini and Antonio A Quijano. Implementação de microcontrolador 8051 reconfigurável em FPGA Remy Eskinazi, Onesimo Ximenes and João Paulo Parallel Communication Architecture based on Microcontrollers for P-Systems Simulation Abraham Gutierrez and Jesus Bobadilla Implementação de uma Unidade de Ponto Flutuante para uma Arquitetura Reconfigurável Mateus Silva, Bruno Hecktheuer, Julio Mattos, Antonio Beck Filho, Mateus Rutzig and Luigi Carro Propuesta didáctica para la enseñanza de arquitecturas de procesadores con lógica programable José A. Rapallini, Héctor Hugo Mazzeo, Walter Aroztegui and Antonio A. Quijano Projeto de uma FPU considerando Área, Frequência e Potência Gracieli Posser, Ricardo Reis and Sergio Bampi Especificação em LOTOS de requisitos de QoS para Redes-em-Chip Dayanne K. F. Rocha, Karla D. N. Ramos and Claudia M. F. Araujo Ribeiro Verificação Funcional Aplicada a Redes-em-Chip Pablo Pires and Cesar Zeferino Ferramenta ASTRAN: para Geração Automática de Circuitos VLSI Felipe Nesello, Charles Leonhardt, Adriel Ziesemer and Ricardo Reis Paralização do Posicionador PlaceDL através de primitivas OpenMP Lucas Cavalheiro, Felipe Pinto and Ricardo Reis Roteamento detalhado usando Pathfinder e A* Charles Leonhardt, Felipe Nesello, Adriel Ziesemer and Ricardo Reis |
| 16:30 to 18:10 |
Session i4 - VIDEO CODING Controlador DDR SDRAM Multicanal de Alta Velocidade Aplicado à Decodificação H.264/AVC Alexsandro Cristovão Bonatto, André Borin Soares and Altamiro Amadeu Susin Arquitetura em Hardware para a Estimação de Movimento de Blocos de Tamanhos Variáveis do Padrão H.264/AVC Roger Porto, Luciano Agostini and Sergio Bampi An H.264 Deblocking Filter in FPGA with RGB Video Output Vagner Rosa, Leandro Silva and Sergio Bampi Avaliação de Eficiência e Desenvolvimento de Arquiteturas de Calculadores de SSD Segundo o Padrão H.264/AVC Felipe Sampaio, Gustavo Sanchez, Robson Dornelles and Luciano Agostini Desenvolvimento de uma Arquitetura para Interpolação de Half-Pixels segundo o padrão H.264/AVC Marcel Corrêa, Mateus Schoenknecht, Robson Dornelles and Luciano Agostini Session i5 - CAD TOOLS 2 Synthesis by Direct Mapping of Asynchronous Controllers from Extended Burst-Mode Specification Duarte Oliveira, Lidia Shibuya and Osamu Saotome A Technique for Accurate Capacitance Ratio Measurements in CMOS Integrated Circuits Antonio Petraglia and Carlos Fernando Teodósio Soares On Structure of the Control Vector for Minimal-Time Circuit Design Process Alexander Zemliak and Miguel Torres Síntese Multiobjetivo de Sistema Composto por Elementos Multifuncionais Adriane Belle, Alice Tokarnia and José R, de Oliveira Influencia de la caracterización en el flujo de diseño de circuitos CMOS nanométricos Gashaw Sassaw Teshome, Carlos Jesús Jiménez Fernández and Manuel Valencia Barrero Session i6 - ANALOG DESIGN 2 Local biasing of negative feedback amplifiers via a graph-theory approach Arturo Sarmiento Reyes, Miguel Angel Gutierrez de Anda, Luis Hernandez Martinez, Ma. Teresa Sanz and Hector Yair González Ramos Redes Mobile MOS-NDR Operando con Reloj de una Fase Juan Nuñez, María J. Avedillo and José M. Quintana Methodology to Improve the Functional Verification of Analog Mixed Signal Circuits Jofre Bartnik and Jose Luis Gomez-Cipriano Analysis and Optimization of a DAR IMPATT Diode for High Frequency Part of Millimetric Region Alexander Zemliak and Santiago Cabrera Design Issues and Experimental Characterization of a Continuously-Tuned Adaptive CMOS LNA Edwin Becerra-Alvarez, Federico Sandoval-Ibarra and Jose M. de la Rosa |
| Wednesday: February 24th | |
| 9:00 to 10:00 | Nano-architectures for Tera-scale systems Keynote Speaker: Giovanni De Micheli - EPFL, Switzerland |
| 10:30 to 12:10 |
Session i7 - DIGITAL DESIGN 1 Procesador para la Emulación de Circuitos Cuánticos basados en Compuertas Toffoli Jorge Duarte-Sanchez, John Michael Espinosa-Duran and Jaime Velasco-Medina A General-Purpose Hardware Implementation of a SVM-SMO Algorithm Jonas Gomes Filho, Raul Acosta Hernandez, Marius Strum and Jiang Chau Wang Implementation of the JasPer Encoder in a NIOS II Processor Jaime Andres Arteaga-Molina and Jaime Velasco-Medina Codiseño Hardware-Software de Sistemas de Control Difusos Sobre FPGAS Santiago Sánchez Solano, María Brox Jiménez, Ernesto del Toro Hernández and Alejandro Cabrera Sarmiento A Comparison between Hardware and Software Full Duplex Internet Protocol Version 4 Implementations Lucas Teixeira, Paulo César Comassetto de Aguirre and Crístian Müller Session i8 - DIGITAL SIGNAL PROCESSING Heuristic-Based Algorithms for the Ordering and Partitioning of the Coefficients in FIR Filter Architectures Angelo Luz, Eduardo Costa and Marilton Aguiar Architectural Exploration in the Butterflies of the Radix-2 Decimation in Time FFT Algorithm Mateus B. Fonseca, Eduardo A. C. da Costa and João B. dos S. Martins Implementation of Split-Radix Fast Fourier Transform on FPGA Cynthia Watanabe, Joel Muñoz and Carlos Silva Sistema para el Tratamiento de Interferencia de 60 Hz y Desplazamiento de la línea de Base del ECG Implementado en Plataformas DSP Javier Enrique Gonzàlez Barajas and Jaime Barrero Diseño e Implementacion de Algoritmos para el Cálculo de la Entropía en DSP para el Estudio Señales Electroencefalográficas Javier Enrique Gonzàlez Barajas, Iván Torres and Andrés Granados |
| 14:00 to 15:15 |
Embedded Tutorial 1 3D-CMOS Neuromorphic Imager with Cortical Layer Interconnects Pedro Julian, UNS, Argentina |
| 15:15 to 16:15 | POSTER SECTION 2 Metodología orientada a la elección de FPGAs con prioridad en el consumo de potencia Jose Miguel Mora Gutierrez, Gashaw Sassaw Teshome, Carlos Jesús Jiménez Fernández and Manuel Valencia Barrero Energy-Aware System Level Evaluation Method for Coarse-grained Hybrid VLIW Architectures Gustavo Adolfo Cerezo Vásquez and Wilhelmus A. M. van Noije Diseño de un Criptoprocesador RSA de 8192 bits usando un Multiplicador Sistólico Claudia Patricia Renteria, Vladimir Trujillo-Olaya and Jaime Velasco-Medina Implementação de uma Unidade em Ponto Flutuante para Operações Aritméticas em FPGA Iuri Castro, Raphael Neves, Alessandro Girardi, Jeferson Marques, Edson Schlosser, Dion Lenon Prediger and Sidinei Ghissoni Especificação em LOTOS de requisitos de QoS para Redes-em-Chip Dayanne K. F. Rocha, Karla D. N. Ramos and Claudia M. F. Araujo Ribeiro Verificação Funcional Aplicada a Redes-em-Chip Pablo Pires and Cesar Zeferino A Multi-parent Genetic Algorithm for Searching for the Pair of Inputs that Cause the Maximum Number of Switching Gates in a Combinational Circuit Norimasa Yamada and Alberto Palacios Pawlovsky Diseño de una Estación de Bombeo Controlada por Computadora para la Caracterización de Estructuras Microfluídicas Houari Cobas Gomez, Marcio Rodrigues da Cunha, Izabela Dutra Alvim, José E. Eirez Izquierdo, Sonnia Pavoni Oliver and Mario R Gongora-Rubio Estudo e Simulação de um Acelerômetro MEMS Carolina Metzler, Ricardo Reis and Gilson Wirth Diseño de un Microsistema usando FPGAs para Medir el Área de una Lamina de Cuero Jhohann Fabian Salazar and Jaime Velasco-Medina Chip para el análisis de parámetros sanguíneos Matias Namiot, Alejandro Mut, José A. Rapallini and Antonio A Quijano |
| 16:15 to 17:55 |
Session i9 - DIGITAL DESIGN 2 Circuitos Integrados para la Enseñanza de Electrónica Jose Daza, Antonio Garcia and Lorena Garcia Gestión del Diseño de Circuitos/Sistemas Monochip Maria Isabel Schiavon, Daniel Alberto Crepaldo and Raúl Lisandro Martín An Educational NoC-based MP-SoC Reconfigurable Platform Targeted to FPGA Implementation Ivan Saraiva Silva, Tadeu Ferreira de Oliveira and Miklecio Bezerra da Costa Implementação e Avaliação de um MPSoC Homogêneo Interconectado por NoC Odair Moreira and Fernando Moraes Implementación sobre FPGA de un cliente SNTP usando MicroBlaze Juan Quiros, Julian Viejo, Alejandro Muñoz, Alejandro Millan, Enrique Ostua and J. Ignacio Villar Session i10 - MEMS AND NANOELECTRONICS Detección de nanoestructuras con el AFM basado en diapasón de cuarzo Juan Pablo Ruiz, John Alexander Aponte and Alba Avila Micromaquinado Superficial con Polisilicio y su Aplicación en Microestructuras Joule Fernando Quiñones Novelo and Wilfrido Calleja-Arriaga Energy Harvesting from Low Amplitude Mechanical Vibrations Using a Piezoelectric Transducer Adilson Jair Cardoso and Carlos Galup Montoro Desarrollo de un Procedimiento para la Fabricación de Microcanales en PDMS Andres Gaona Barrera, David Olea and Dora Ballesteros Concepcion y Puesta a Punto de un Micro-Sistema para el Estudio de Estructuras Biologicas Mediante Impedancia Electrica Paul Tiburcio and Jordi Aguilò |
|
Thursday: February 25th |
|
| 9:00 to 10:00 |
Block-Based Transceivers for Wireless Networks Invited Talk: Paulo Diniz - UFRJ, Brazil |
| 10:30 to 12:10 | Session i11 - DIGITAL DESIGN 3 Acelerador em Hardware para Resolução do Despacho de Métodos Polimórficos em Programas Java Tomás Garcia Moreira, Daniel Guimarães Júnior, Marco Aurélio Wehrmeister, Carlos Eduardo Pereira and Ricardo Reis Controlador de Procesos Dinámicos a Partir de Modelos Difusos Interpretables Luis Murillo and Juan Contreras Asynchronous Pipeline Digital Design using FPGA Implementation Duarte Oliveira and Eduardo Lussari Revisiting clock-gating: the Common Place for Power Reduction Javier Castro, Pilar Parra and Antonio Acosta Synthesis of Low-Power Synchronous Controllers Operating with Local Clock Duarte Oliveira and Luiz Sergio Ferreira Session i12 - NOC AND MPSOC Utilizando protótipos virtuais para avaliação do impacto do DMA no desempenho de sistemas MPSoC Marcelo Schuck, Marcio Oyamada and Maxiwell Garcia Hierarquia de Memória em MPSoC Baseado em NoC - Implementação e Avaliação Fernando Moraes and Tales Chaves A Simulation Methodology for a NoC-Based Dynamically Reconfigurable System Mario Raffo, Wang Jiang Chau and Marius Strum An Hybrid Switching Approach for NoC-Based Systems to avoid Denial-of-Service SoC Attacks Martha Johanna Sepulveda, Marius Strum and Wang Jiang Desenvolvimento de Aplicação com Requisitos de QoS para SoC baseado em NoC Douglas Melo, Marcelo Berejuck and Cesar Zeferino |
| 14:00 to 15:15 |
Embedded Tutorial 2: Integrated systems security: hardware-based threats and solutions Regis Leveugle - TIMA, France |
| 15:15 to 16:15 |
POSTER SECTION 3 Circuito de Polarización con independencia de Tensión de Alimentación y cancelación parcial del efecto de la temperatura Pablo Petrashin, Walter Lancioni, Luis Toledo and Carlos Vazquez Sistema de Monitoramento de Qualidade de Energia Elétrica em Baixa Tensão Carlos Eduardo Fusinatto Magnani, Carlos Eduardo Maffini Santos, Ivan Jorge Chueiri and Valter Klein Jr. Corrector del Factor de Potencia de Desplazamiento para Instalaciones Eléctricas de Baja Tensión Enrique Montoya Suarez System of quality monitoring and faults in the network of secondary power lines Valter Klein Jr., Ivan Jorge Chueiri, Carlos Eduardo Fusinatto Magnani and Carlos Eduardo Maffini Santos Estado del arte de las redes de sensores inalámbricos (wsn) Federico Fernández and Juan Carlos Fabero Neuronal and Programmable Circuit with Floating-Gate Transistor Multiple Input Four Bits Alejandro Medina Santiago and Mario Alfredo Reyes Barranca Using statistical simulations for improving IIP2 in direct conversion receivers Antonio Felipe Freitas Silva, Fernando Sousa and Sebastian Catunda Implementação de um Multiplicador Sobre GF(2^4) Utilizando Portas de Limiar Linear Cristóvão Filho, Alan Sá, Karolie Nobre, Raimundo Freire and Francisco Marcos Diseño de una Arquitectura para la Solución de la Ecuación de Schrödinger usando el Método de Numerov Victor Alfonso Rodriguez-Toro, Fabio Noguera-Leon and Jaime Velasco-Medina Dispositivo Electrónico para la Medición de Variables Biomédicas Correlacionadas en la Inferencia de Estrés Antonio Garcia and Juan David Fonseca A Mixed-Signal Interface for Low-Cost Sensors in Battery-Operated Multisensor Systems Alberto Bayo, Nicolás Medrano, Belén Calvo, Santiago Celma, María Teresa Sanz and Arturo Sarmiento Desarrollo de un Dispositivo Inalámbrico para la Estimación del Gasto Energético por Actividad Física Mediante Acelerometría Daniel Lupi, Sergio Gwirc, Diego Brengi, Fernando Marsilli and Christian Huy |
| 16:15 to 17:55 | Session i13 - FPGA BASED DESIGN Implementações em FPGA do Protocolo de Sincronização e Codificação de Canal de Telemetria recomendado pelo CCSDS Fábio B. Armelin and Roberto d'Amore A Reed-Solomon CODEC for OTN G.709 Standard with Reduced Decoder FPGA Area Tiago Barbosa, Robson Moreno and Tales Pimenta. An FPGA Implementation of a Kernel Function for Support Vector Machines Jonas Gomes Filho, Raul Acosta Hernandez, Marius Strum and Jiang Chau Wang FPGA implementation: A multiple-stage converter control for a pulsed current source Nicolas Wassinger, Rogelio Garcia Retegui, Marcos Funes and Mario Benedetti Estocasticidad de un atractor caótico determinista implementado en FPGA Luciana De Micco, Omar G. Zabaleta, Claudio M. Gonzalez, Constancio M. Arizmendi and Hilda Angela Larrondo Session i14 - WIRELESS AND CRYPTOGRAPHY TLM and VHDL-AMS Co-Simulation of a System on Chip for Wireless Sensor Networks Gilmar S. Beserra, Juan F. Eusse, João V. B. Pimentel, Arthur M. Sampaio, Ricardo P. Jacobi and José C. da Costa Sistema de medida en ambientes industriales basado en redes de sensores inalámbricos Alfonso González, Natacha Leone, Mauricio Murdoch, Pablo Mazzara and Julián Oreggioni Diseño en Hardware para los cifradores de flujo Grain-128, Mickey-128, Decim-128 y Trivium Juan Manuel Marmolejo, Vladimir Trujillo-Olaya and Jaime Velasco-Medina Hardware Architectures for Inversion in GF(2m) Vladimir Trujillo-Olaya and Jaime Velasco-Medina. |
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LASCAS 2010 Program
Wednesday: February 24th |
|
| 9:00 to 10:00 | Nano-architectures for Tera-scale systems Keynote Speaker: Giovanni De Micheli - EPFL, Switzerland |
| 10:30 to 12:10 |
Session L1 Digital Control System Using a Thermoelectric Cell for Temperature Electronic Devices Testing João Bazzo, Jean Carlos Cardozo da Silva, Emerson Geovani Carati, Marcio Vogt and Tiago Lukasievicz. A Fuzzy Control for Optimizing the Design of Passive Electrical Circuits N. Hernández-Romero, P.A. Miranda-Romagnoli and J.C. Seck-Tuoh-Mora. On Restoring Data Coherence in a GALS System for Medical Imaging Carlos Leong, João Teixeira, Isabel Teixeira, Pedro Machado, Vasco Bexiga, Ricardo Bugalho, Miguel Ferreira, Pedro Rodrigues, José Silva, João Varela and Pedro Lousã. IMAGE INTERPOLATION USING COSINE-SINE MODULATED FILTER BANK Shusnuke Iwamura, Seisuke Kyochi, Naoto Kaneko and Masaaki Ikehara Hardware/Software Implementation of an on-line Machine Learning Algorithm Carlos Quintero, Lorena Garcia, Fernando Lozano and Mauricio Guerrero. Session L2 - Data Converters Design of a 12.5 GS/s 5-bit Folding A/D Converter Antonio Surano and Franco Maloberti. A Clock-less 8-bit A/D Converter Sabiniano Araujo Rodrigues, Jose Ivan Carnauba Accioly, Hassan Aboushady, Marie-Minerve Louerat and Raimundo Carlos Silverio Freire. A noise-insensitve offset calibration technique for time interleaved SAR ADC Ding Li, Sin Sai Weng, U Seng Pan and Rui Martins. An Area-Efficient Coarse-Fine Resistor-String D/A Converter Byung-Do Yang, Young-Kyu Shin, Keun-Chul Ryu, Jae-Joong Min, Si-Woo Sung and Jae-Mun Oh. An Architecture for First-Order Tunable Mismatch Shaping in Oversampled Data Converters Waqas Akram and Earl E. Swartzlander, Jr.. |
| 14:00 to 15:15 |
Embedded Tutorial 1 3D-CMOS Neuromorphic Imager with Cortical Layer Interconnects Pedro Julian, UNS, Argentina |
| 16:15 to 17:55 | Session L3 Design Methodology for ZCT and ZCZVT Inverters Jean Gazzoni, Cristiano Piva, Paulo Ferla, Carlos Stein and Mario Martins An Energy Based LQR Tuning Approach Applied for Uninterruptible Power Supplies João Marcos Kanieski, Emerson Giovani Caratti and Rafael Cardoso A hardware DC Motor emulator Vagner Rosa, Vitor Gervini, Sebastiao Gomes and Sergio Bampi. A Lightweight Mechanism for Dynamic Linking in Wireless Sensor Networks Carlo Brandolese, Luigi Rucco and William Fornaciari. A 128 FFT Core Implementation for Multiband Full-Rate Ultra-Wideband Receivers Bruno Fernandes and Helena Sarmento. Session L4 - RF Amplifiers A Novel Notch Filter LNA for Use in Multi-Band, Multi-Standard Cellular Receivers Dirk Bormann, Stefan Kaehlert, Tobias D. Werth and Stefan Heinen. A Fully Integrated 65 nm CMOS cascode HSFDS PA Dedicated to 802.11n Application Yohann luque, Eric Kerhervé, Nathalie Deltimple and Didier Belot. Characterization Methodology of a Millimeter-Wave 65nm CMOS PA Dedicated to 60GHz WPAN Standard Sofiane Aloui, Nicolas Delaunay, Eric Kerherve, Nathalie DELTIMPLE, Robert Plana and Didier Belot. Automatic Design of RF Linear Transconductor Diomadson Belfort. Low Voltage High performance Current Mirrors Prateek Vajpayee, A. Srivastava, S. S. Rajput and G. K. Sharma. |
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POSTER SECTION 1 Analog Circuits All-Pass Filter Employing Fully Balanced Voltage Differencing Buffered Amplifier Dalibor Biolek, Viera Biolkova and Zdenek Kolka. Incorporating Effects of Process, Voltage, and Temperature Variation in BTI Model for Circuit Design Shreyas Kumar Krishnappa, Harwinder Singh and Hamid Mahmoodi. Ultra Low-Power Super Class AB CMOS OTA Cells with Rail-to-Rail Operation Mahdi Ahangarian Abhari, adib Abrishamifar and Seyed Javad Azhari. A Framework for Circuit-Level Analog Synthesis With an Educational Approach Tiago Oliveira Weber and Cesar Ramos Rodrigues. RF Circuits Differential Continuous-Time Delta Sigma Modulator using the FGMOS Transistor Jesus de la Cruz and Noe Oliva. Design of Hardware Accelerators for Demanding Applications Lech Jozwiak and Yahya Jan An efficient technique to design linear-phase decimation filters David Ernesto Troncoso Romero and Gordana Jovanovic Dolecek. Formula Simplification using Two-Graph Method Zdenek Kolka, Martin Vlk, Dalibor Biolek, Viera Biolkova and Josef Dobes. |
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Thursday: February 25th |
|
| 9:00 to 10:00 |
Block-Based Transceivers for Wireless Networks Invited Talk: Paulo Diniz - UFRJ, Brazil |
| 10:30 to 12:10 | Session L5 An Experimental Study of Interconnection Length in 3D and 2D VLSI Prasun Ghosal, Hafizur Rahaman and Parthasarathi Dasgupta Piecewise Linear-based Hybrid Simulation of MOS and Single-Electron Circuits Arturo Sarmiento, Francisco Javier Castro, Luis Hernández-Martínez and Miguel Angel Gutiérrez. Optimized Large Size Signed Multipliers and Applications in FPGAs Shuli Gao, Dhamin Al-Khalili and Noureddine Chabini. A Parallel Architecture for Ray-Tracing for FPGA Implementation Alexandre Nery, Nadia Nedjah and Felipe M. G. França. Implementing and testing the FPGA prototype of a DCM demodulator using the Matlab/Simulink environment Mário Véstias, Hugo Santos and Helena Sarmento. Session L6 - DAC and Bio Applications Accurate Multi-bit Feedback DAC Dedicated to High-speed Continuous-time delta-sigma Converters Andre Mariano, Cédric Majek, Dominique Dallet, Yann Deval and Jean-Baptiste Begueret. A Short-Channel Silicon-Based Split-Drain MAGFET Measuring from 90 μT Gerard Santillan, Victos Champac and Roberto Murphy. How can Electrosurgical Sparks generate Undesirable Effects? Bertoldo Schneider Jr., Elton Dias Jr. and Paulo José Abatti. A Carbon Nanotube Spiking Cortical Neuron with Tunable Refractory Period and Spiking Duration Jonathan Joshi, Alice C. Parker and Chih-Chieh Hsu. Selectable Gain Amplifier for Inductive Sensor used to measure Human Motion Gustavo Theodoro Laskoski, Sérgio Francisco Pichorim and Paulo José Abatti. |
| 14:00 to 15:15 |
Embedded Tutorial 2: Integrated systems security: hardware-based threats and solutions Regis Leveugle - TIMA, France |
| 15:15 to 16:15 |
POSTER SECTION 2 Impact of different power reduction techniques at architectural level on modern FPGAs Henryk Błasiński, Frederic Amiel and Thomas Ea Master-Slave Flip-flop Optimization for fine-grained clock-gating Applications Javier Castro, Pilar Parra and Antonio Acosta. A new architecture for a FM modulator based on time-varying eigenvalues Miguel Angel Gutierrez de Anda, Arturo Sarmiento Reyes and Alfonso Prieto Guerrero. NOTIFY: a Network-On-chip-based Tool to Inject Faults extensivelY Hananeh Aliee and Hamid R. Zarandi. Source-Level Energy Estimation and Optimization of Embedded Software Carlo Brandolese, William Fornaciari and Daniele Scarpazza A Fuzzy Model for Network Traffic Prediction Using Orthonormal Basis Functions Based on Multifractal Characteristics Flávio H. T. Vieira, Flávio G. C. Rocha, Scheila G. Garcez and Christiane B. Santos. ASIC Implementation of a Parser Module for a Minimalist H.264 Video Decoder Leandro Silva, Fabio Pereira and Sergio Bampi. A Comparison of Steady-State Procedures Based on Epsilon-Algorithm and Sensitivity Analysis Josef Dobes, David Cerny, Viera Biolkova and Zdenek Kolka. Time-Stamp of Digital Audio Recording Based on the ENF Estimated from Another Audio Signal Isabela Apolinario and Carlos Rossi. Evaluating the Efficiency of Software-only Techniques to Detect SEU and SET in Microprocessors José Rodrigo Azambuja, Fernando Sousa, Lucas Rosa and Fernanda Lima Kastensmidt. High Efficiency Reference Frames Storage for H.264/AVC Decoder Hardware Implementation Alexsandro C. Bonatto, Andre B. Soares and Altamiro A. Susin. A Study on Clock Mesh Size Selection Guilherme Flach, Gustavo Wilke, Marcelo Johann and Ricardo Reis. Cascode dynamic current calibration: A new scheme for implementation of highly accurate current memories Jaime Ramirez-Angulo, Enrique Lopez-Morillo, Ramon G. Carvajal and Antonio J. Lopez-Martin. |
| 16:15 - 17:40 | Session L7 Motion Vector Predictor Architecture for H.264/AVC Main Profile Targeting HDTV 1080p Franco Valdez, Bruno Zatt, Arnaldo Azevedo, Luciano Agostini and Sergio Bampi. A MIPS-based ASIP to Accelerate the Inverse Hadamard Tranform for H.264/AVC Video Coding Gracieli Posser, Guilherme Corrêa, Ricardo Reis, Luigi Carro and Sergio Bampi. Comparative Analysis of Parallel SAD Calculation Hardware Architectures for H.264/AVC Video Coding Cláudio Diniz, Guilherme Corrêa, Altamiro Susin and Sergio Bampi. Analysis of the Conditions for Worst Case Switching Activity in Integrated Circuits Carlos Sampaio, Jose Monteiro and L. Miguel Silveira. |
| 16:15 to 17:40 |
Special Session Biomedical Circuit & Systems Development of a Signal Acquisition Platform for Respiratory Assistance Antonio García Rozo, Diego Méndez Chávez, Lina Peñuela, Jaime Rivera and Jorge Torres Impact of parasitic capacitances on the performance of SAR ADCs based on capacitive arrays Alberto Rodríguez-Pérez, José A. Rodríguez, Fernando Medeiro and Manuel Delgado-Restituto A CMOS QFG ECG amplifier with baseline stabilization Antonio Lopez-Martin, Jaime Ramirez-Angulo, Ramon G. Carvajal Design of a versatile voltage based output stage for implantable neural stimulators Marijn N. van Dongen and Wouter A. Serdijn |
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Friday: February 26th |
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| 9:00 to 10:00 |
Ultra-low power logic circuits: From voltage-mode to current-mode Invited Talk: Massimo Alioto - Italy |
| 10:30 to 12:10 |
Session L8 Stepped Triangular CIC Decimation Filter for SDR Applications Gordana Jovanovic Dolecek and Alfonso Fernandez- Vazquez. On the Normalized Minimum Error-Entropy Adaptive Algorithm: Cost Function and Update Recursion Wallace Martins, Paulo Diniz and Yih-Fang Huang. Cross-Layer Constrained Power Management: Application to a Multimedia Mobile Platform William fornaciari, Patrick Bellasi, David Siorpaes, Stefano Bosisio and Matteo Carnevali. Delay Sensing for Parametric Variations and Defects Monitoring in Safety-Critical Applications Júlio Vazquez, Victor Champac, Adriel Ziesemer Jr., Ricardo Reis, Isabel Teixeira, Marcelino Santos and Paulo Teixeira Traffic Modeling and Analysis of PLC Networks using Markov Chains Christiane Borges Santos, Flávio Henrique Teles Vieira, Sergio Granato de Araújo, Fabio da Silva Marques, João Batista José Pereira, Flavio Geraldo C. Rocha and Dominique Carvalho Fernandes. Session L9 - Analog Circuits Design of a high-sensitivity sub-40ug capacitive accelerometer using a Multi-Project Wafer process André Keller Abadie and Roberto d'Amore. A Simple Approach for the Design of Operational Transconductance Amplifiers for Low Power Signal Processing Alfonso Chacón-Rodríguez, Santiago Sondon, Pablo Mandolesi and Pedro Julián. Offset-Compensated Comparator with Full-Input Range in 150nm FDSOI CMOS-3D Technology Manuel Suarez, Victor Brea, Carlos Domínguez, Ricardo Carmona, Gustavo Liñán and Angel Rodríguez Vázquez. A New Readout Circuit for Infrared Imaging Sensors Gholamreza Akbarizadeh and Gholam Ali Rezai-rad. Practical Considerations for the Design of Fully Differential OTAs with SC-CMFB Carlos Bula and Manuel Jimenez. |
| 14:00 to 15:15 |
Embedded Tutorial 3: Modeling Interconnect and Design-in Passives for Efficient Coupled Analysis Luis Miguel Silveira - INESC-ID, Portugal |
| 15:45 -17:25 |
Session L10 Cache Alternatives Concerning Cache Coherence in NoC-based MPSoC Platform Ivan Saraiva Silva, Bruno Cruz de Oliveira and Gustavo Girão. Grayscale CNN Computation of Boolean Functions Eero Lehtonen, Jussi Poikonen, Jonne Poikonen and Mika Laiho. A Study on the Propagation Times of Loaded CMOS Inverters Sergio Vale Pires, Manuel Dionisio Rolo, Ernesto Ventura Martins and Luis Nero Alves. Multi-Threaded Circuit Simulation using OpenMP Mark Zwolinski A Modified Izhikevich Model For Circuit Implementation of Spiking Neural Networks Arash Ahmadi and Mark Zwolinski. Session L11 Impact of Compilation Options on the Criticality of Registers in a Microprocessor-based System Salma Bergaoui and Regis Leveugle. A New Automated Instrumentation for Emulation-based Fault Injection Regis Leveugle and Adrien Prost-Boucle. Performance Evaluation of Hybrid ANN Based Time Series Prediction on Embedded Processor Rafael Trapani Possignolo and Omar Hamammi. Design and Simulation of a Unit Cell for a QWIP-FPA Lester de Abreu Faria, Fabio Durante Pereira Alves and Newton Gomes. |