UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL
INSTITUTO DE INFORMÁTICA
PROGRAMA DE POS-GRADUAÇÃO EM COMPUTAÇÃO
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DEFESA DE DISSERTAÇÃO DE MESTRADO

Aluno: Débora da Silva Motta Matos
Orientador: Prof. Dr. Altamiro Amadeu Susin

Coorientadora: Prof. Dr. Luigi Carro

Titulo: Exploring Hierarchy, Adaptability and 3D in NoCs for the Next Generation of MPSoCs
Linha de Pesquisa: Arquitetura e Projeto de Sistemas Computacionais

Data: 15/10/2013
Hora:  13h30min
Local: Sala 218. Prédio 43412 – Instituto de Informática

Banca Examinadora:
Prof. Dr. Cesar Albenes Zeferino (UNIVALI)
Profa. Dra. Fernanda Gusmão de Lima Kastensmidt (UFRGS)
Profa. Dra. Martha Johanna Sepúlveda Flórez (USP) – Por videoconferência

Profa. Dra. Monica Magalhães Pereira (UFRN)

Presidente da Banca: Prof. Dr. Altamiro Amadeu Susin

Resumo: he demand for systems with high performance brought the need to increase the number of processing elements, emerging the called Multi-Processors Systems-on-Chip (MPSoCs). In this manner, with the reduction of the technological scale, it was possible to integrate tens of devices in a single chip. However, with the increase of these ele-ments, another concern about how these devices communicate and are connected has been raised, since these features are essential for the performance, energy and power aspects of the application. This need allows the advent of the Networks-on-Chip (NoCs) and countless studies were already done to analyze such interconnect devices. However, due to the current technological accelerating that brings the need for even more complex systems, consuming low energy and providing constant application updates without losing the performance features, other interconnect alternatives need to be investigated. Several proposals to attend such requirements are evidenced and will be presented in this work, such as: hierarchical, adaptive and three dimensions interconnections. This work approaches the requirements in the use of different strategies for NoCs in order to reach the requisites of performance and low power of the current and future MPSoCs. Hence, in this approach, several interconnect architectures for heterogeneous systems, their scalability and the main features and advantages of the proposed strategies in comparison with others will be verified.

Palavras-chave: Network-on-chip, hierarchical topology, crossbar, circuit switching, packet switching, 3D designs, 3D interconnects.