UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL
INSTITUTO DE INFORMÁTICA
PROGRAMA DE POS-GRADUAÇÃO EM COMPUTAÇÃO
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DEFESA DE DISSERTAÇÃO DE MESTRADO

Aluno: Kleber Hugo Stangherlin
Orientador: Prof. Dr. Sergio Bampi
Coorientador: Prof. Dr. Valter Roesler

Titulo: Energy and Speed Exploration in Digital CMOS Circuits in the Near-threshold Regime for Very-Wide Voltage-Frequency Scaling
Linha de Pesquisa: Microeletrônica

Data:  16/09/2013
Hora:  14h
Local: Auditório Inferior. Prédio 43413(67) – Instituto de Informática

Banca Examinadora:
Prof. Dr. Renato Perez Ribas (UFRGS)
Prof. Dr. Ricardo Augusto da Luz Reis (UFRGS)
Prof. Dr. Volnei Antonio Pedroni (UTFPR)

Presidente da Banca: Prof. Dr. Sergio Bampi

Resumo: This thesis assesses the benefits and drawbacks associated with a very wide range of frequency when operation at near-threshold is considered. Scaling down the supply voltage in digital CMOS circuits presents great benefits in terms of power reduction. Such scaling comes with a performance penalty, hence in digital synchronous circuits the reduction in frequency of operation follows, for a given circuit layout, the VDD reduction.

Minimum-energy operation of digital CMOS circuits is commonly associated to the sub-VT regime, carrying huge performance and variability penalties. This thesis shows that it is possible to achieve 8X higher energy-efficiency with a very-wide range of dynamic voltage-frequency scaling, from nominal voltages down to the lower boundary of near-VT operation. As part of this study, a CMOS digital cell-library for such wide range of frequencies was developed.

The cell-library is exercised in a 65nm commercial PDK and targets near-VT operation, mitigating the variability effects without compromising the design in terms of area and energy at strong inversion. For near-VT or sub-VT operation the cells have to be designed with few stacked transistors. Our study shows that good performance in terms of static-noise margins is obtained for a constrained set of cells, for which a maximum of 2-stacked transistors are allowed. In this set we include master-slave registers.

We report results for medium complexity designs which include a 25kgates notch filter, a 20kgates 8051 compatible core, and 4-combinational/4-sequential ISCAS benchmark circuits. In this work the maximum frequency attainable at each supply for a wide variation of voltage is studied from 150mV up to nominal voltage (1.2V). The sub-VT operation is shown to hold the minimum energy-point at roughly 0.29V, which represents a 2X energy-saving  compared to the near-VT regime. Although energy-efficiency peaks in sub-VT for the circuits studied, we also show that in this ultra-low Vdd the circuit timing and power suffer from substantially increased variability impact and a 30X performance drawback, with respect to near-VT.

Palavras-chave: voltage-frequency scaling, energy-efficiency, power savings, near-threshold.