Publicado em: 05/03/2013

Proposta de Tese em Processamento Paralelo e Distribuído

UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL
INSTITUTO DE INFORMÁTICA
PROGRAMA DE PÓS-GRADUAÇÃO EM COMPUTAÇÃO
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DEFESA DE PROPOSTA DE TESE

Aluno: Marco Antonio Zanata Alves
Orientador: Prof. Dr. Philippe Olivier Alexandre Navaux

Título: Increasing Energy Efficiency of Processor Caches via Line Usage Predictors
Linha de Pesquisa: Processamento Paralelo e Distribuído

Data: 11/03/2013
Horário: 14h
Local: Auditório José Mauro Volkmer de Castilho, Prédio 43424 – Instituto de Informática

Banca Examinadora:
Prof. Dr. Luigi Carro (UFRGS)
Prof. Dr. Flávio Rech Wagner (UFRGS)
Prof. Dr. Edson Borin (UNICAMP)

Presidente da Banca: Prof. Dr. Philippe Olivier Alexandre Navaux

Resumo:
To deliver high performance, current CMP integrate large caches in order to reduce the average memory access latency by allocating the applications’ working set on-chip. These cache memories have traditionally been designed to exploit temporal locality by using replacement policies, and spatial locality by fetching entire cache lines from memory on a cache miss.
However, recent studies have shown that the number of sub-blocks within a line that are actually used is often low, and those sub-blocks that are used are accessed only a few times before becoming dead (that is, never accessed again). Additionally, many of the cache lines remain powered for a long period of time even if the data is not used again, or is invalid. For dirty cache lines, the LLC waits until the line is evicted to perform the write-back to memory. These dirty lines compete with read requests (cache prefetch and processor demand), increasing the memory pressure on the memory controller.
This thesis introduces cache line usage predictors to increase the energy efficiency of cache memories. We propose the DSBP and DEWP mechanisms to enable energy savings without performance degradation.

Palavras-chave: Line Usage Predictors, Cache Memories, Energy Efficient