No dia 05 de abril às 13:30h (Horário de Brasília) ocorrerá a palestra “Physical Design on Transistor Level Beyond Standard Cell Methodology” com Renato Hentchke – Senior Software Architect da Synopsys (USA).
Para acessar a palestra, clique aqui.
YouTube Live @ IEEE CASS Rio Grande do Sul Chapter
Abstract:
This talk offers a review of possibilities to explore on VLSI layout beyond traditional standard cell methodology. Existing Physical Design tools strictly avoid any modification to the contents of Standard Cells. Here, a post-processing step based on SAT solvers is proposed to obtain optimal solutions for local transistor level layout synthesis problems. This procedure can be constrained by metrics that ensure that quality is not degraded, and an acceptable and better-quality timing model can be rebuilt for the block. These problems and techniques are open research opportunities in Physical Design as they are not sufficiently explored in the literature and can bring significant improvements to the quality of a VLSI circuit.
Short CV:
Renato is currently a Senior Architect at Synopsys. He holds Bachelors, Master and PhD degrees in computer science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Through his entire career, Renato specialized in VLSI Physical Design algorithms for problems such as placement, routing and related layout challenges. In 2004, Renato joined IBM Research in T. J. Watson Research Center as in intern for 10 months working on timing driven routing and placement driven synthesis. In 2007 Renato joined Intel Corporation where he stayed for 13 years working in design rule modeling, design rule abstraction, routing and standard cell synthesis. Among other honors, Renato received an Intel Achievement Award in recognition for his contributions to routing automation of the Broadwell project (14nm processor). In 2020 Renato joined Synopsys Inc. working with layout automation and DTCO. Renato currently has 45 published papers with 646 citations.